Datasheet

RESET Operations

Table 30: Reset Command Set

Command Command Code (Binary) Command Code (Hex) Address Bytes

RESET ENABLE 0110 0110 66 0

RESET MEMORY 1001 1001 99 0

RESET ENABLE and RESET MEMORY Command

To reset the device, the RESET ENABLE command must be followed by the RESET

MEMORY command. To execute each command, S# is driven LOW. The command code

is input on DQ0. A minimum de-selection time of

SHSL2 must come between the RE-

SET ENABLE and RESET MEMORY commands or a reset is not guaranteed. When these

two commands are executed and S# is driven HIGH, the device enters a power-on reset

condition. A time of

SHSL3 is required before the device can be re-selected by driving

S# LOW. It is recommended that the device exit XIP mode before executing these two

commands to initiate a reset.

If a reset is initiated while a WRITE, PROGRAM, or ERASE operation is in progress or

suspended, the operation is aborted and data may be corrupted.

Figure 34: RESET ENABLE and RESET MEMORY Command

DQ0

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

Reset enable Reset memory

Note:

1. The number of lines and rate for transmission varies with extended, dual, or quad SPI.

RESET Conditions

All volatile lock bits, the volatile configuration register, the enhanced volatile configura-

tion register, and the extended address register are reset to the power-on reset default

condition. The power-on reset condition depends on settings in the nonvolatile config-

uration register.

3V, 256Mb: Multiple I/O Serial Flash Memory

RESET Operations

09005aef84566603

n25q_256mb_65nm.pdf - Rev. W 11/16 EN

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