Datasheet

Terminating XIP After a Controller and Memory Reset

The system controller and the device can become out of synchronization if, during the

life of the application, the system controller is reset without the device being reset. In

such a case, the controller can reset the memory to power-on reset if the memory has

reset functionality. (Reset is available in devices with a dedicated part number.)

If reset functionality is not available, has been disabled, or is not supported by the con-

troller, the controller must execute the following sequence to terminate XIP in the

memory device. In quad I/O protocol, drive DQ0 = 1 with S# held LOW for seven clock

cycles; S# must driven HIGH before the eighth clock cycle. In dual I/O protocol, drive

DQ0 = 1 with S# held LOW for 13 clock cycles; S# must driven HIGH before the four-

teenth clock cycle. If the device is in extended protocol, drive DQ0 = 1 with S# held LOW

for 25 clock cycles; S# must driven HIGH before the twenty-sixth clock cycle.

These sequences cause the controller to set the XIP confirmation bit to 1, thereby termi-

nating XIP. However, it does not reset the device or interrupt PROGRAM/ERASE opera-

tions that may be in progress. After terminating XIP, the controller must execute RESET

ENABLE and RESET MEMORY to implement a software reset and reset the device.

3V, 256Mb: Multiple I/O Serial Flash Memory

XIP Mode

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n25q_256mb_65nm.pdf - Rev. W 11/16 EN

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