Datasheet

Power Up and Power Down
Power Up and Power Down Requirements
At power-up and power-down, the device must not be selected; that is, S# must follow
the voltage applied on V
CC
until V
CC
reaches the correct values: V
CC,min
at power-up and
V
SS
at power-down.
To avoid data corruption and inadvertent WRITE operations during power-up, a power-
on reset circuit is included. The logic inside the device is held to RESET while V
CC
is less
than the power-on reset threshold voltage shown here; all operations are disabled, and
the device does not respond to any instruction. During a standard power-up phase, the
device ignores all commands except READ STATUS REGISTER and READ FLAG STATUS
REGISTER. These operations can be used to check the memory internal state. After
power-up, the device is in standby power mode; the write enable latch bit is reset; the
write in progress bit is reset; and the lock registers are configured as: (write lock bit, lock
down bit) = (0,0).
Normal precautions must be taken for supply line decoupling to stabilize the V
CC
sup-
ply. Each device in a system should have the V
CC
line decoupled by a suitable capacitor
(typically 100nF) close to the package pins. At power-down, when V
CC
drops from the
operating voltage to below the power-on-reset threshold voltage shown here, all opera-
tions are disabled and the device does not respond to any command.
Note: If power-down occurs while a WRITE, PROGRAM, or ERASE cycle is in pro-
gress, data corruption may result.
V
PPH
must be applied only when V
CC
is stable and in the V
CC,min
to V
CC,max
voltage
range.
Figure 38: Power-Up Timing
V
CC
V
CC,min
V
WI
Chip
reset
Chip selection not allowed
Polling allowed
t
VTW =
t
VTR
Time
Device fully accessible
V
CC,max
SPI protocol
Starting protocol
defined by NVCR
WIP = 1
WEL = 0
WIP = 0
WEL = 0
3V, 256Mb: Multiple I/O Serial Flash Memory
Power Up and Power Down
09005aef84566603
n25q_256mb_65nm.pdf - Rev. W 11/16 EN
72
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