Datasheet

Table 34: Power-Up Timing and V

Threshold

Note 1 applies to entire table

Symbol Parameter Min Max Unit

VTR V

CC,min

to read – 150 µs

VTW V

CC,min

to device fully accessible – 150 µs

Write inhibit voltage 1.5 2.5 V

Note:

1. Parameters listed are characterized only.

Power Loss Recovery Sequence

If a power loss occurs during a WRITE NONVOLATILE CONFIGURATION REGISTER

command, after the next power-on, the device might begin in an undetermined state

(XIP mode or an unnecessary protocol). If this occurs, until the next power-up, a recov-

ery sequence must reset the device to a fixed state (extended SPI protocol without XIP).

After the recovery sequence, the issue should be resolved definitively by running the

WRITE NONVOLATILE CONFIGURATION REGISTER command again. The recovery se-

quence is composed of two parts that must be run in the correct order. During the en-

tire sequence,

SHSL2 must be at least 50ns. The first part of the sequence is DQ0 (PAD

DATA) and DQ3 (PAD HOLD) equal to 1 for the situations listed below:

• 7 clock cycles within S# LOW (S# becomes HIGH before 8th clock cycle)

• + 9 clock cycles within S# LOW (S# becomes HIGH before 10th clock cycle)

• + 13 clock cycles within S# LOW (S# becomes HIGH before 14th clock cycle)

• + 17 clock cycles within S# LOW (S# becomes HIGH before 18th clock cycle)

• + 25 clock cycles within S# LOW (S# becomes HIGH before 26th clock cycle)

• + 33 clock cycles within S# LOW (S# becomes HIGH before 34th clock cycle)

The second part of the sequence is exiting from dual or quad SPI protocol by using the

following FFh sequence: DQ0 and DQ3 equal to 1 for 8 clock cycles within S# LOW; S#

becomes HIGH before 9th clock cycle.

After this two-part sequence the extended SPI protocol is active.

Initial Delivery Status

The device is delivered as follows:

• Memory array erased: All bits are set to 1 (each byte contains FFh)

• Status register contains 00h (all status register bits are 0)

• Nonvolatile configuration register (NVCR) bits all erased (FFFFh)

3V, 256Mb: Multiple I/O Serial Flash Memory

Initial Delivery Status

09005aef84566603

n25q_256mb_65nm.pdf - Rev. W 11/16 EN

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