Datasheet

Figure 39: Reset AC Timing During PROGRAM or ERASE Cycle
t
SHRH
t
RLRH
t
RHSL
S#
RESET#
Don’t Care
Figure 40: Reset Enable
C
S#
DQ0
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
Reset enable Reset memory
t
SHSL2
t
SHSL3
Figure 41: Serial Input Timing
t
SLCH
t
CHSL
t
DVCH
t
CHDX
t
CLCH
t
CHCL
t
CHSH
t
SHCH
t
SHSL
S#
C
DQ0
DQ1
High-Z High-Z
MSB in LSB in
Don’t Care
3V, 256Mb: Multiple I/O Serial Flash Memory
AC Reset Specifications
09005aef84566603
n25q_256mb_65nm.pdf - Rev. W 11/16 EN
75
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