Datasheet

Rev. M – 09/12

• Added clarification notes to Signal Assignments

Rev. L – 08/12

• Additional note to Command Set table in Command Definitions

• Corrections to Commands in Command Definitions

Rev. K – 07/12

• Added I

CC1

(grade 3) to DC Characteristics and Operating Conditions

• Removed READ FLAG STATUS related notes from Command Definitions

• Added N25Q256A13EF8A0x, N25Q256A13ESFA0x, N25Q256A13ESFH0x,

N25Q256A13E12A0x to Features

Rev. J – 06/12

• Typo fix in Supported Clock Frequencies – DTR table in Nonvolatile and Volatile Reg-

isters

• Updated

SSE specification in AC Reset Conditions table

• Added N25Q256A83ESF40x and N25Q256A83E1240x to Features

• Added RESET pin and functionality throughout

Rev. I – 01/12

• Updated DUAL INPUT/OUTPUT FAST READ - DTR third code and added note 11;

added note 12 to QUAD INPUT/OUTPUT FAST READ - DTR in the Command Set ta-

ble

• Updated V

min and max specs in the Power-Up Timing and V

Threshold table

Rev. H – 11/11

• Updated Supported Clock Frequencies – STR in Nonvolatile and Volatile Registers

Rev. G – 07/11

• Added double transfer rate (DTR) mode information

Rev. F – 07/11

• Miscellaneous edits, including correction of V-PDFN 8 x 6 package and clarification of

feature set option 7.

Rev. E – 05/11

• Added W# to logic diagram in Device Description

• Cross-reference update to Status Register Bit Definitions table

• Added dummy clock and quad SPI protocol information to Command Definitions

notes

• Corrected Manufacturer ID values

• Removed extraneous frequency requirement note from READ IDENTIFICATIONS Op-

erations

3V, 256Mb: Multiple I/O Serial Flash Memory

Revision History

09005aef84566603

n25q_256mb_65nm.pdf - Rev. W 11/16 EN

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