User manual

The three boot modes are described in the following sections.
3.1 microSD Boot Mode
The Arty Z7 supports booting from a microSD card inserted into connector J9. The following
procedure will allow you to boot the Zynq from microSD with a standard Zynq Boot Image
created with the Xilinx tools:
1. Format the microSD card with a FAT32 file system.
2. Copy the Zynq Boot Image created with Xilinx SDK to the microSD card.
3. Rename the Zynq Boot Image on the microSD card to BOOT.bin.
4. Eject the microSD card from your computer and insert it into connector J9 on the Arty
Z7.
5. Attach a power source to the Arty Z7 and select it using JP5.
6. Place a single jumper on JP4, shorting the two top pins (labeled “SD”).
7. Turn the board on. The board will now boot the image on the microSD card.
3.2 Quad SPI Boot Mode
The Arty Z7 has an onboard 16MB Quad-SPI Flash that the Zynq can boot from. Documentation
available from Xilinx describes how to use Xilinx SDK to program a Zynq Boot Image into a
Flash device attached to the Zynq. Once the Quad SPI Flash has been loaded with a Zynq Boot
Image, the following steps can be followed to boot from it:
1. Attach a power source to the Arty Z7 and select it using JP5.
2. Place a single jumper on JP4, shorting the two center pins (labeled “QSPI”).
3. Turn the board on. The board will now boot the image stored in the Quad SPI flash.
3.3 JTAG Boot Mode
When placed in JTAG boot mode, the processor will wait until software is loaded by a host
computer using the Xilinx tools. After software has been loaded, it is possible to either let the
software begin executing, or step through it line by line using Xilinx SDK.
It is also possible to directly configure the PL over JTAG, independent of the processor. This can
be done using the Vivado Hardware Server.
The Arty Z7 is configured to boot in Cascaded JTAG mode, which allows the PS to be accessed
via the same JTAG port as the PL. It is also possible to boot the Arty Z7 in Independent JTAG
mode by loading a jumper in JP2 and shorting it. This will cause the PS to not be accessible from
the onboard JTAG circuitry, and only the PL will be visible in the scan chain. To access the PS
over JTAG while in independent JTAG mode, users will have to route the signals for the PJTAG
peripheral over EMIO, and use an external device to communicate with it.