User manual

Both the memory chips and the PS DDR bank are powered from the 1.5V supply. The mid-point
reference of 0.75V is created with a simple resistor divider and is available to the Zynq as
external reference.
For proper operation it is essential that the PS memory controller is configured properly. Settings
range from the actual memory flavor to the board trace delays. For your convenience, the Zynq
presets file for the Arty Z7 is provided on the resource center and automatically configures the
Zynq Processing System IP core with the correct parameters.
For best DDR3 performance, DRAM training is enabled for write leveling, read gate, and read
data eye options in the PS Configuration Tool in Xilinx tools. Training is done dynamically by
the controller to account for board delays, process variations and thermal drift. Optimum starting
values for the training process are the board delays (propagation delays) for certain memory
signals.
Board delays are specified for each of the byte groups. These parameters are board-specific and
were calculated from the PCB trace length reports. The DQS to CLK Delay and Board Delay
values are calculated specific to the Arty Z7 memory interface PCB design.
For more details on memory controller operation, refer to the Xilinx Zynq Technical Reference
manual.
¹Maximum actual clock frequency is 525 MHz on the Arty Z7 due to PLL limitation.
6 USB UART Bridge (Serial Port)
The Arty Z7 includes an FTDI FT2232HQ USB-UART bridge (attached to connector J14) that
lets you use PC applications to communicate with the board using standard COM port commands
(or the tty interface in Linux). Drivers are automatically installed in Windows and newer
versions of Linux. Serial port data is exchanged with the Zynq using a two-wire serial port
(TXD/RXD). After the drivers are installed, I/O commands can be used from the PC directed to
the COM port to produce serial data traffic on the Zynq pins. The port is tied to PS (MIO) pins
and can be used in combination with the UART 0 controller.
The Zynq presets file (available in the Arty Z7 Resource Center) takes care of mapping the
correct MIO pins to the UART 0 controller and uses the following default protocol parameters:
115200 baud rate, 1 stop bit, no parity, 8-bit character length.
Two on-board status LEDs provide visual feedback on traffic flowing through the port: the
transmit LED (LD11) and the receive LED (LD10). Signal names that imply direction are from
the point-of-view of the DTE (Data Terminal Equipment), in this case the PC.