User manual

The Zynq incorporates two independent Gigabit Ethernet Controllers. They implement a
10/100/1000 half/full duplex Ethernet MAC. Of these two, GEM 0 can be mapped to the MIO
pins where the PHY is connected. Since the MIO bank is powered from 1.8V, the RGMII
interface uses 1.8V HSTL Class 1 drivers. For this I/O standard an external reference of 0.9V is
provided in bank 501 (PS_MIO_VREF). Mapping out the correct pins and configuring the
interface is handled by the Arty Z7 Zynq Presets file, available on the Arty Z7 Resource Center.
Although the default power-up configuration of the PHY might be enough in most applications,
the MDIO bus is available for management. The RTL8211E-VL is assigned the 5-bit address
00001 on the MDIO bus. With simple register read and write commands, status information can
be read out or configuration changed. The Realtek PHY follows industry-standard register map
for basic configuration.
The RGMII specification calls for the receive (RXC) and transmit clock (TXC) to be delayed
relative to the data signals (RXD[0:3], RXCTL and TXD[0:3], TXCTL). Xilinx PCB guidelines
also require this delay to be added. The RTL8211E-VL is capable of inserting a 2ns delay on
both the TXC and RXC so that board traces do not need to be made longer.
The PHY is clocked from the same 50 MHz oscillator that clocks the Zynq PS. The parasitic
capacitance of the two loads is low enough to be driven from a single source.
On an Ethernet network each node needs a unique MAC address. To this end, the one-time-
programmable (OTP) region of the Quad-SPI flash has been programmed at the factory with a
48-bit globally unique EUI-48/64™ compatible identifier. The OTP address range [0x20;0x25]
contains the identifier with the first byte in transmission byte order being at the lowest address.
Refer to the Flash memory datasheet for information on how to access the OTP regions. When
using Petalinux, this is automatically handled in the U-boot boot-loader, and the Linux system is
automatically configured to use this unique MAC address.
For more information on using the Gigabit Ethernet MAC, refer to the Zynq Technical Reference
manual.
10 HDMI
The Arty Z7 contains two unbuffered HDMI ports: one source port J11 (output), and one sink
port J10 (input). Both ports use HDMI type-A receptacles with the data and clock signals
terminated and connected directly to the Zynq PL.
Both HDMI and DVI systems use the same TMDS signaling standard, directly supported by
Zynq PL's user I/O infrastructure. Also, HDMI sources are backward compatible with DVI sinks,
and vice versa. Thus, simple passive adaptors (available at most electronics stores) can be used
to drive a DVI monitor or accept a DVI input. The HDMI receptacle only includes digital
signals, so only DVI-D mode is possible.