User manual

The XADC core within the Zynq is a dual channel 12-bit analog-to-digital converter capable of
operating at 1 MSPS. Either channel can be driven by any of the analog inputs connected to the
shield pins. The XADC core is controlled and accessed from a user design via the Dynamic
Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present
on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For
more information on using the XADC core, refer to the Xilinx document titled “7 Series FPGAs
and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital
Converter”. It is also possible to access the XADC core directly using the PS, via the “PS-
XADC” interface. This interface is described in full in chapter 30 of the Zynq Technical
Reference manual.
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https://reference.digilentinc.com/reference/programmable‐logic/arty‐z7/reference‐manual