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DS187 (v1.19) October 3, 2016 www.xilinx.com

Product Specification 1

in the United States and other countries. AMBA, AMBA Designer, ARM, Cortex-A9, CoreSight, Cortex, PrimeCell, ARM Powered, and ARM Connected Partner are trademarks

of ARM Ltd. All other trademarks are the property of their respective owners.

Introduction

The Zynq®-7000 All Programmable SoCs are available in -3,

-2, -1, and -1LI speed grades, with -3 having the highest

performance. The -1LI devices can operate at either of two

programmable logic (PL) V

CCINT

CCBRAM

voltages, 0.95V

and 1.0V, and are screened for lower maximum static power.

The speed specification of a -1LI device is the same as the -1

speed grade. When operated at PL V

CCINT

CCBRAM

= 0.95V,

the -1LI static and dynamic power is reduced. Zynq-7000

device DC and AC characteristics are specified in

commercial, extended, industrial and expanded (Q-temp)

temperature ranges. Except for the operating temperature

range or unless otherwise noted, all the DC and AC electrical

parameters are the same for a particular speed grade (that

is, the timing characteristics of a -1 speed grade industrial

device are the same as for a -1 speed grade commercial

device). However, only selected speed grades and/or

devices are available in the commercial, extended,

industrial, or Q-temp temperature ranges.

All supply voltage and junction temperature specifications

are representative of worst-case conditions. The parameters

included are common to popular designs and typical

applications.

The available device/package combinations are outlined in:

• Zynq-7000 All Programmable SoC Overview (DS190)

• XA Zynq-7000 All Programmable SoC Overview (DS188

)

• Defense-grade Zynq-7000Q All Programmable SoC

Overview (DS196

)

This Zynq-7000 AP SoC data sheet, which covers the

specifications for the XC7Z007S, XC7Z012S, XC7Z014S,

XC7Z010, XA7Z010, XC7Z015, XC7Z020, XA7Z020, and

XQ7Z020, complements the Zynq-7000 AP SoC

documentation suite available on the Xilinx website at

www.xilinx.com/zynq

DC Characteristics

Zynq-7000 All Programmable SoC

(Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020):

DC and AC Switching Characteristics

DS187 (v1.19) October 3, 2016 Product Specification

Table 1: Absolute Maximum Ratings

(1)

Symbol Description Min Max Units

Processing System (PS)

CCPINT

PS internal logic supply voltage –0.5 1.1 V

CCPAUX

PS auxiliary supply voltage –0.5 2.0 V

CCPLL

PS PLL supply –0.5 2.0 V

CCO_DDR

PS DDR I/O supply voltage –0.5 2.0 V

CCO_MIO

(2)

PS MIO I/O supply voltage –0.5 3.6 V

PREF

PS input reference voltage –0.5 2.0 V

(2)(3)(4)(5)

PS MIO I/O input voltage –0.40 V

CCO_MIO

+0.55 V

PS DDR I/O input voltage –0.55 V

CCO_DDR

+0.55 V

Programmable Logic (PL)

CCINT

PL internal supply voltage –0.5 1.1 V

CCAUX

PL auxiliary supply voltage –0.5 2.0 V

CCBRAM

PL supply voltage for the block RAM memories –0.5 1.1 V

CCO

PL supply voltage for HR I/O banks –0.5 3.6 V

REF

Input reference voltage –0.5 2.0 V

Summary of content (72 pages)

PAGE 1
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020): DC and AC Switching Characteristics DS187 (v1.19) October 3, 2016 Product Specification Introduction The Zynq®-7000 All Programmable SoCs are available in -3, -2, -1, and -1LI speed grades, with -3 having the highest performance. The -1LI devices can operate at either of two programmable logic (PL) VCCINT/VCCBRAM voltages, 0.95V and 1.0V, and are screened for lower maximum static power.
PAGE 2
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 1: Absolute Maximum Ratings(1) (Cont’d) Symbol Description Min Max Units I/O input voltage for HR I/O banks –0.40 VCCO + 0.55 V VIN(3)(4)(5) I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards except TMDS_33(6) –0.40 2.625 V VCCBATT Key memory battery backup supply –0.5 2.
PAGE 3
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 2: Recommended Operating Conditions(1)(2) (Cont’d) Symbol VPIN(4) Description Min Typ Max Units PS DDR and MIO I/O input voltage –0.20 – VCCO_DDR + 0.20 VCCO_MIO + 0.20 V PL internal supply voltage 0.95 1.00 1.05 V PL -1LI (0.95V) internal supply voltage 0.92 0.95 0.98 V PL auxiliary supply voltage 1.71 1.80 1.89 V PL block RAM supply voltage 0.95 1.00 1.05 V PL -1LI (0.
PAGE 4
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 3: DC Characteristics Over Recommended Operating Conditions Symbol Description Min Typ(1) Max Units VDRINT Data retention VCCINT voltage (below which configuration data might be lost) 0.75 – – V VDRI Data retention VCCAUX voltage (below which configuration data might be lost) 1.
PAGE 5
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 4: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for PS I/O and PL HR I/O Banks(1)(2) AC Voltage Overshoot % of UI @–40°C to 125°C VCCO + 0.55 AC Voltage Undershoot % of UI @–40°C to 125°C –0.40 100 –0.45 61.7 –0.50 25.8 –0.55 11.0 100 VCCO + 0.60 46.6 –0.60 4.77 VCCO + 0.65 21.2 –0.65 2.10 VCCO + 0.70 9.75 –0.70 0.94 VCCO + 0.75 4.55 –0.75 0.43 VCCO + 0.80 2.15 –0.80 0.
PAGE 6
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 5: Typical Quiescent Supply Current (Cont’d) Symbol ICCDDRQ ICCINTQ ICCAUXQ ICCOQ Description PS quiescent VCCO_DDR supply current PL quiescent VCCINT supply current PL quiescent VCCAUX supply current PL quiescent VCCO supply current DS187 (v1.
PAGE 7
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 5: Typical Quiescent Supply Current (Cont’d) Symbol ICCBRAMQ Description PL quiescent VCCBRAM supply current Device Speed Grade Units -3 -2 -1 -1LI XC7Z007S N/A 3 3 N/A mA XC7Z012S N/A 4 4 N/A mA XC7Z014S N/A 6 6 N/A mA XC7Z010 3 3 3 1/2(4) mA XC7Z015 4 4 4 2/2(4) mA XC7Z020 6 6 6 3/4(4) mA XA7Z010 N/A N/A 3 N/A mA XA7Z020 N/A N/A 6 N/A mA XQ7Z020 N/A 6 6
PAGE 8
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) PS Power-On/Off Power Supply Sequencing The recommended power-on sequence is VCCPINT, then VCCPAUX and VCCPLL together, then the PS VCCO supplies (VCCO_MIO0, VCCO_MIO1, and VCCO_DDR) to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on.
PAGE 9
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Power Supply Requirements Table 6 shows the minimum current, in addition to ICCQ, that is required by Zynq-7000 devices for proper power-on and configuration. If the current minimums shown in Table 5 and Table 6 are met, the device powers on after all four PL supplies have passed through their power-on reset threshold voltages. The Zynq-7000 device must not be configured until after VCCINT is applied.
PAGE 10
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) DC Input and Output Levels Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH voltage levels shown.
PAGE 11
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) PL I/O Levels Table 10: SelectIO DC Input and Output Levels(1)(2) I/O Standard VIL VIH VOL VOH IOL IOH V, Min V, Max V, Min V, Max V, Max V, Min mA mA HSTL_I –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 8.00 –8.00 HSTL_I_18 –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 8.00 –8.00 HSTL_II –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.
PAGE 12
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 12: Complementary Differential SelectIO DC Input and Output Levels I/O Standard VICM(1) VID(2) V, Min V,Typ V, Max V,Min V, Max VOL(3) VOH(4) IOL IOH V, Max V, Min mA, Max mA, Min DIFF_HSTL_I 0.300 0.750 1.125 0.100 – 0.400 VCCO–0.400 8.00 –8.00 DIFF_HSTL_I_18 0.300 0.900 1.425 0.100 – 0.400 VCCO–0.400 8.00 –8.00 DIFF_HSTL_II 0.300 0.750 1.125 0.100 – 0.400 VCCO–0.400 16.
PAGE 13
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) AC Switching Characteristics All values represented in this data sheet are based on the speed specifications in the ISE® Design Suite 14.7 and Vivado® Design Suite 2015.4 as outlined in Table 14. Table 14: Zynq-7000 All Programmable SoC Speed Specification Version By Device ISE 14.7 Vivado 2016.3 Device 1.08 1.11 XC7Z010 and XC7Z020 N/A 1.11 XC7Z007S, XC7Z012S, XC7Z014S, and XC7Z015 1.06 1.
PAGE 14
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 15: Zynq-7000 Device Speed Grade Designations (Cont’d) Speed Grade Designations Device Advance Preliminary Production XC7Z020 -3E, -2E, -2I, -1C, -1I, -1LI XA7Z010 -1I, -1Q XA7Z020 -1I, -1Q XQ7Z020 -2I, -1I, -1Q, -1LI Production Silicon and Software Status In some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label
PAGE 15
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) To select the -1LI (PL 0.95V) speed specifications in the Vivado tools, select the Zynq-7000 sub-family and then select the part name that is the device name followed by an i followed by the package name followed by the speed grade. For example, select the xc7z020iclg484-1L part name for the XC7Z020 device in the CLG484 package and -1LI (PL 0.95V) speed grade. The -1LI (PL 0.
PAGE 16
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) PS Switching Characteristics Clocks Table 20: System Reference Clock Input Requirements Symbol Description Min Typ Max Units TJTPSCLK PS_CLK RMS clock jitter tolerance – – ±0.
PAGE 17
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 23: PS Reset/Power Supply Timing Requirements Symbol TSLW(1) Description PS_CLK Frequency (MHz) Min Max Units 30 12 39 ms 33.33 12 40 ms 60 13 40 ms 30 –32 13 ms 33.33 –27 13 ms 60 –9 25 ms 30 –19 9 ms 33.33 –16 12 ms 60 –3 25 ms 30 –830 –788 ms 33.33 –746 –705 ms 60 –408 –374 ms 128 KB CRC eFUSE disabled and PLL enabled.
PAGE 18
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 26: DDR3 Interface Switching Characteristics (800 Mb/s)(1) Symbol Description Min Max Units TDQVALID(2) Input data valid window 500 – ps TDQDS(3) Output DQ to DQS skew 232 – ps TDQDH(4) Output DQS to DQ skew 401 – ps TDQSS Output clock to DQS skew –0.10 0.
PAGE 19
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 28: DDR3L Interface Switching Characteristics (800 Mb/s)(1) (Cont’d) Symbol TCKCA(6) Description Command/address output hold time with respect to CLK Min Max Units 853 – ps Notes: 1. 2. 3. 4. 5. 6. Recommended VCCO_DDR = 1.35V ±5%. Measurement is taken from VREF to VREF. Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.
PAGE 20
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 31: DDR2 Interface Switching Characteristics (800 Mb/s)(1) Symbol Description Min Max Units TDQVALID(2) Input data valid window 500 – ps TDQDS(3) Output DQ to DQS skew 147 – ps TDQDH(4) Output DQS to DQ skew 376 – ps TDQSS Output clock to DQS skew –0.07 0.
PAGE 21
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) X-Ref Target - Figure 2 CLK CLK TCKCA TCACK Write Command NOP NOP NOP NOP TCKCA TCACK Address Bank, Col n TDQSS DQS DQS TDQDH TDQDH TDQDS TDQDS D0 DQ D1 D2 D3 DS187_01_012213 Figure 2: DDR Output Timing Diagram X-Ref Target - Figure 3 CLK CLK DQS DQS DQ TDQVALID D0 D1 D2 D3 DS187_02_012213 Figure 3: DDR Input Timing Diagram DS187 (v1.19) October 3, 2016 Product Specification www.xilinx.
PAGE 22
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Static Memory Controller Table 33: SMC Interface Delay Characteristics(1)(2) Symbol Description Min Max Units TNANDDOUT NAND_IO output delay from last register to pad 4.12 6.45 ns TNANDALE NAND_ALE output delay from last register to pad 5.08 6.33 ns TNANDCLE NAND_CLE output delay from last register to pad 4.87 6.40 ns TNANDWE NAND_WE_B output delay from last register to pad 4.69 5.
PAGE 23
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Quad-SPI Interfaces Table 34: Quad-SPI Interface Switching Characteristics Symbol Description Load Conditions Min Max Units All(1)(2) 44 56 % 15 pF(1) –0.10(3) 2.30 30 pF(2) –1.00 3.80 15 pF(1) 2.00 – 30 pF(2) 3.30 – 15 pF(1) 1.30 – 30 pF(2) 1.
PAGE 24
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) X-Ref Target - Figure 4 QSPI{1,0}_SS_B TQSPICLKSS1 TQSPISSCLK1 QSPI_SCLK_OUT CPOL = 0 TQSPICLKSS1 TQSPISSCLK1 QSPI_SCLK_OUT CPOL = 1 TQSPICKD1 TQSPICKO1 QSPI{1,0}_IO_[3,0] OUT0 TQSPIDCK1 OUT1 INn-2 INn-1 INn DS187_03_110515 Figure 4: Quad-SPI Interface (Feedback Clock Enabled) Timing Diagram X-Ref Target - Figure 5 QSPI{1,0}_SS_B TQSPICLKSS2 TQSPISSCLK2 QSPI_SCLK_OUT (CPOL = 0) TQSPISSCLK2 TQSPICLKSS2 QS
PAGE 25
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) ULPI Interfaces Table 35: ULPI Interface Clock Receiving Mode Switching Characteristics(1)(2) Symbol Description Min Typ Max Units TULPIDCK Input setup to ULPI clock, all inputs 3.00 – – ns TULPICKD Input hold to ULPI clock, all inputs 1.00 – – ns TULPICKO ULPI clock to output valid, all outputs 1.70 – 8.86 ns FULPICLK ULPI device clock frequency – 60 – MHz Notes: 1. 2.
PAGE 26
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) RGMII and MDIO Interfaces Table 36: RGMII and MDIO Interface Switching Characteristics(1)(2)(3) Symbol Description Min Typ Max Units 45 – 55 % TDCGETXCLK Transmit clock duty cycle TGEMTXCKO RGMII_TX_D[3:0], RGMII_TX_CTL output clock to out time –0.50 – 0.50 ns TGEMRXDCK RGMII_RX_D[3:0], RGMII_RX_CTL input setup time 0.80 – – ns TGEMRXCKD RGMII_RX_D[3:0], RGMII_RX_CTL input hold time 0.
PAGE 27
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) SD/SDIO Interfaces Table 37: SD/SDIO Interface High Speed Mode Switching Characteristics(1) Symbol Description Min Typ Max Units – 50 – % TDCSDHSCLK SD device clock duty cycle TSDHSCKO Clock to output delay, all outputs 2.00 – 12.00 ns TSDHSDCK Input setup time, all inputs 3.00 – – ns TSDHSCKD Input hold time, all inputs 1.
PAGE 28
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) I2C Interfaces Table 39: I2C Fast Mode Interface Switching Characteristics(1) Symbol Description Min Typ Max Units TDCI2CFCLK I2C{0,1}SCL duty cycle – 50 – % TI2CFCKO I2C{0,1}SDAO clock to out delay – – 900 ns TI2CFDCK I2C{0,1}SDAI setup time 100 – – ns FI2CFCLK I2C{0,1}SCL clock frequency – – 400 KHz Notes: 1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
PAGE 29
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) SPI Interfaces Table 41: SPI Master Mode Interface Switching Characteristics(1) Symbol Description Min Typ Max Units TDCMSPICLK SPI master mode clock duty cycle – 50 – % TMSPIDCK Input setup time for SPI{0,1}_MISO 2.00 – – ns TMSPICKD Input hold time for SPI{0,1}_MISO 8.20 – – ns TMSPICKO Output delay for SPI{0,1}_MOSI and SPI{0,1}_SS –3.10 – 3.
PAGE 30
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 42: SPI Slave Mode Interface Switching Characteristics(1)(2) Symbol Description Min Max Units TSSPIDCK Input setup time for SPI{0,1}_MOSI and SPI{0,1}_SS 1 – FSPI_REF_CLK cycles TSSPICKD Input hold time for SPI{0,1}_MOSI and SPI{0,1}_SS 1 – FSPI_REF_CLK cycles TSSPICKO Output delay for SPI{0,1}_MISO 0 2.
PAGE 31
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) CAN Interfaces Table 43: CAN Interface Switching Characteristics(1) Symbol Description Min Max Units TPWCANRX Minimum receive pulse width 1 – µs TPWCANTX Minimum transmit pulse width 1 – µs Internally sourced CAN reference clock frequency – 100 MHz Externally sourced CAN reference clock frequency – 40 MHz Min Max Units FCAN_REF_CLK Notes: 1.
PAGE 32
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) GPIO Interfaces Table 46: GPIO Banks Switching Characteristics(1) Symbol Description Min Max Units TPWGPIOH Input high pulse width 10 x 1/cpu1x – µs TPWGPIOL Input low pulse width 10 x 1/cpu1x – µs Notes: 1. Pulse width requirement for interrupt.
PAGE 33
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) PL Performance Characteristics This section provides the performance characteristics of some common functions and designs implemented in the PL. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same guidelines as the AC Switching Characteristics, page 13.
PAGE 34
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) PL Switching Characteristics IOB Pad Input/Output/3-State Table 52 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard), and 3-state delays. • TIOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO input buffer.
PAGE 35
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 52: IOB High Range (HR) Switching Characteristics (Cont’d) I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade -3 -2 HSTL_I_18_S 0.67 0.75 0.82 0.88 1.29 1.41 1.67 1.67 1.31 1.44 1.68 1.68 ns HSTL_II_18_S 0.66 0.75 0.81 0.88 1.41 1.54 1.79 1.79 1.43 1.57 1.80 1.80 ns DIFF_HSTL_I_S 0.68 0.76 0.83 0.86 1.59 1.71 1.96 1.96 1.60 1.74 1.98 1.
PAGE 36
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 52: IOB High Range (HR) Switching Characteristics (Cont’d) I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade -3 -2 LVCMOS18_F24 0.74 0.83 0.89 0.97 1.34 1.46 1.71 2.28 1.35 1.49 1.73 2.29 ns LVCMOS15_S4 0.77 0.86 0.93 0.96 2.05 2.18 2.43 2.43 2.07 2.21 2.45 2.45 ns LVCMOS15_S8 0.77 0.86 0.93 0.96 2.09 2.21 2.46 2.46 2.10 2.24 2.48 2.
PAGE 37
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 53: IOB 3-state Output Switching Characteristics Symbol Speed Grade Description -3 -2 -1C/-1I/-1LI -1Q Units TIOTPHZ T input to pad high-impedance 2.06 2.19 2.37 2.37 ns TIOIBUFDISABLE IBUF turn-on time from IBUFDISABLE to O output 2.11 2.30 2.60 2.
PAGE 38
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 54: Input Delay Measurement Methodology (Cont’d) Description I/O Standard Attribute VL (1)(2) VH(1)(2) VMEAS VREF (1)(4)(6) (1)(3)(5) LVDS_25, 2.5V LVDS_25 1.2 – 0.125 1.2 + 0.125 0(6) – BLVDS_25, 2.5V BLVDS_25 1.25 – 0.125 1.25 + 0.125 0(6) – MINI_LVDS_25, 2.5V MINI_LVDS_25 1.25 – 0.125 1.25 + 0.125 0(6) – PPDS_25 PPDS_25 1.25 – 0.125 1.25 + 0.125 0(6) – RSDS_25 RSDS_25 1.25 – 0.
PAGE 39
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using this method: 1. Simulate the output driver of choice into the generalized test setup using values from Table 55. 2. Record the time to VMEAS. 3.
PAGE 40
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 55: Output Delay Measurement Methodology (Cont’d) Description I/O Standard Attribute RSDS_25 RSDS_25 TMDS_33 TMDS_33 RREF (Ω) CREF(1) (pF) VMEAS (V) VREF (V) 100 0 0(2) 0 0 0(2) 3.3 50 Notes: 1. 2. CREF is the capacitance of the probe, nominally 0 pF. The value given is the differential output voltage.
PAGE 41
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 57: OLOGIC Switching Characteristics (Cont’d) Symbol TOTCECK/ TOCKTCE Speed Grade Description TCE pin setup/hold with respect to CLK Units -3 -2 -1C/-1I/-1LI -1Q 0.32/0.01 0.34/0.01 0.51/0.01 0.51/0.01 ns 0.83 0.96 1.16 1.16 ns Combinatorial D1 to OQ out or T1 to TQ out TODQ Sequential Delays TOCKQ CLK to OQ/TQ out 0.47 0.49 0.56 0.56 ns TRQ_OLOGIC SR pin to OQ/TQ out 0.72 0.80 0.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Output Serializer/Deserializer Switching Characteristics Table 59: OSERDES Switching Characteristics Symbol Speed Grade Description Units -3 -2 -1C/-1I/-1LI -1Q 0.42/0.03 0.45/0.03 0.63/0.03 0.63/0.08 ns 0.69/–0.13 0.73/–0.13 0.88/–0.13 0.88/–0.13 ns 0.31/–0.13 0.34/–0.13 0.39/–0.13 0.39/–0.13 ns 0.32/0.58 0.34/0.58 0.51/0.58 0.51/0.58 ns 0.47 0.52 0.85 0.85 ns 0.32/0.01 0.34/0.01 0.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 60: Input Delay Switching Characteristics (Cont’d) Symbol TIDELAYPAT_JIT and TODELAYPAT_JIT Speed Grade Description Units -3 -2 -1C/-1I/-1LI -1Q Pattern dependent period jitter in delay chain for clock pattern.(2) 0 0 0 0 ps per tap Pattern dependent period jitter in delay chain for random data pattern (PRBS 23)(3) REFCLK 200 MHz ±5 ±5 ±5 ±5 ps per tap REFCLK 300 MHz ±3.33 ±3.33 ±3.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) CLB Switching Characteristics Table 62: CLB Switching Characteristics Symbol Speed Grade Description -3 -2 -1C/-1I/-1LI -1Q Units Combinatorial Delays TILO An – Dn LUT address to A 0.10 0.11 0.13 0.13 ns, Max TILO_2 An – Dn LUT address to AMUX/CMUX 0.27 0.30 0.36 0.36 ns, Max TILO_3 An – Dn LUT address to BMUX_A 0.42 0.46 0.55 0.55 ns, Max TITO An – Dn inputs to A – D Q outputs 0.94 1.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 63: CLB Distributed RAM Switching Characteristics (Cont’d) Symbol Speed Grade Description Units -3 -2 -1C/-1I/-1LI -1Q 0.54/0.28 0.60/0.30 0.72/0.35 0.72/0.37 ns, Min Address An inputs to clock 0.27/0.55 0.30/0.60 0.37/0.70 0.37/0.71 ns, Min Address An inputs through MUXs and/or carry logic to clock 0.69/0.18 0.77/0.21 0.94/0.26 0.94/0.35 ns, Min 0.38/0.10 0.43/0.12 0.53/0.17 0.53/0.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Block RAM and FIFO Switching Characteristics Table 65: Block RAM and FIFO Switching Characteristics Symbol Speed Grade Description Units -3 -2 -1C/-1I/-1LI -1Q Clock CLK to DOUT output (without output register)(2)(3) 1.85 2.13 2.46 2.46 ns, Max Clock CLK to DOUT output (with output register)(4)(5) 0.64 0.74 0.89 0.89 ns, Max Clock CLK to DOUT output with ECC (without output register)(2)(3) 2.77 3.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 65: Block RAM and FIFO Switching Characteristics (Cont’d) Symbol Speed Grade Description -3 -2 -1C/-1I/-1LI -1Q Units TRCCK_EN/ TRCKC_EN Block RAM enable (EN) input 0.35/0.20 0.39/0.21 0.45/0.23 0.45/0.41 ns, Min TRCCK_REGCE/ TRCKC_REGCE CE input of output register 0.24/0.15 0.29/0.15 0.36/0.16 0.36/0.39 ns, Min TRCCK_RSTREG/ TRCKC_RSTREG Synchronous RSTREG input 0.29/0.07 0.32/0.07 0.35/0.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 65: Block RAM and FIFO Switching Characteristics (Cont’d) Symbol Speed Grade Description -3 -2 -1C/-1I/-1LI -1Q Units FMAX_FIFO FIFO in all modes without ECC 509.68 460.83 388.20 388.20 MHz FMAX_ECC Block RAM and FIFO in ECC configuration 410.34 365.10 297.53 297.53 MHz Notes: 1. 2. 3. 4. 5. 6. The timing report shows all of these parameters as TRCKO_DO.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) DSP48E1 Switching Characteristics Table 66: DSP48E1 Switching Characteristics Symbol Speed Grade Description -3 -2 -1C/-1I/-1LI -1Q Units Setup and Hold Times of Data/Control Pins to the Input Register Clock TDSPDCK_A_AREG/ TDSPCKD_A_AREG A input to A register CLK 0.26/0.12 0.30/0.13 0.37/0.14 0.37/0.28 ns TDSPDCK_B_BREG/TDSPCKD_B_BREG B input to B register CLK 0.33/0.15 0.38/0.16 0.45/0.18 0.45/0.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 66: DSP48E1 Switching Characteristics (Cont’d) Symbol TDSPDCK_RSTP_PREG/ TDSPCKD_RSTP_PREG Description RSTP input to P register CLK Speed Grade -3 -2 0.27/0.01 0.30/0.01 Units -1C/-1I/-1LI -1Q 0.35/0.01 0.35/0.03 ns Combinatorial Delays from Input Pins to Output Pins TDSPDO_A_CARRYOUT_MULT A input to CARRYOUT output using multiplier 3.79 4.35 5.18 5.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 66: DSP48E1 Switching Characteristics (Cont’d) Symbol Description Speed Grade -3 -2 -1C/-1I/-1LI -1Q Units Clock to Outs from Input Register Clock to Output Pins TDSPCKO_P_AREG_MULT CLK AREG to P output using multiplier 3.94 4.51 5.37 5.37 ns TDSPCKO_P_BREG CLK BREG to P output not using multiplier 1.64 1.87 2.22 2.22 ns TDSPCKO_P_CREG CLK CREG to P output not using multiplier 1.69 1.93 2.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Clock Buffers and Networks Table 67: Global Clock Switching Characteristics (Including BUFGCTRL) Symbol Speed Grade Description -3 -2 -1C/-1I/-1LI -1Q Units TBCCCK_CE/TBCCKC_CE(1) CE pins setup/hold 0.13/0.39 0.14/0.41 0.18/0.42 0.18/0.84 ns TBCCCK_S/TBCCKC_S(1) S pins setup/hold 0.13/0.39 0.14/0.41 0.18/0.42 0.18/0.84 ns TBCCKO_O(2) BUFGCTRL delay from I0/I1 to O 0.08 0.09 0.11 0.11 ns 628.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 71: Duty-Cycle Distortion and Clock-Tree Skew Symbol TDCD_CLK TCKSKEW Description Device Global clock tree duty-cycle distortion(1) Global clock tree skew(2) Speed Grade Units -3 -2 -1C/-1I/-1LI -1Q All 0.20 0.20 0.20 0.20 ns XC7Z007S N/A 0.27 0.27 N/A ns XC7Z012S N/A 0.39 0.42 N/A ns XC7Z014S N/A 0.38 0.42 N/A ns XC7Z010 0.27 0.27 0.27 N/A ns XC7Z015 0.33 0.39 0.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 72: MMCM Specification (Cont’d) Symbol Speed Grade Description -3 -2 -1C/-1I/-1LI -1Q Units MMCM_TLOCKMAX MMCM maximum lock time 100.00 100.00 100.00 100.00 µs MMCM_FOUTMAX MMCM maximum output frequency 800.00 800.00 800.00 800.00 MHz MMCM_FOUTMIN MMCM minimum output frequency(5)(6) 4.69 4.69 4.69 4.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) PLL Switching Characteristics Table 73: PLL Specification Symbol Speed Grade Description -3 -2 -1C/-1I/-1LI -1Q Units PLL_FINMAX Maximum input clock frequency 800.00 800.00 800.00 800.00 MHz PLL_FINMIN Minimum input clock frequency 19.00 19.00 19.00 19.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Device Pin-to-Pin Output Parameter Guidelines Table 74: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)(1) Symbol Description Device Speed Grade -3 -2 -1C/-1I/-1LI -1Q Units SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flops, Fast Slew Rate, without MMCM/PLL.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 76: Clock-Capable Clock Input to Output Delay With MMCM Symbol Description Speed Grade Device -3 -2 -1C/-1I/-1LI -1Q Units SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flops, Fast Slew Rate, with MMCM. TICKOFMMCMCC Clock-capable clock input and OUTFF with MMCM XC7Z007S N/A 1.03 1.03 N/A ns XC7Z012S N/A 1.04 1.06 N/A ns XC7Z014S N/A 1.04 1.05 N/A ns XC7Z010 1.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Device Pin-to-Pin Input Parameter Guidelines Table 79: Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks Symbol Description Speed Grade Device -3 Units -2 -1C/-1I/-1LI -1Q N/A 2.13/–0.17 2.44/–0.17 N/A ns N/A 2.55/–0.18 3.03/–0.18 N/A ns N/A 2.74/–0.25 3.18/–0.25 N/A ns XC7Z010 2.00/–0.17 2.13/–0.17 2.44/–0.17 N/A ns XC7Z015 2.38/–0.18 2.55/–0.18 3.03/–0.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 81: Clock-Capable Clock Input Setup and Hold With PLL Symbol Description Speed Grade Device -3 -2 -1C/-1I/-1LI -1Q Units Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 Standard.(1) TPSPLLCC/ TPHPLLCC No delay clock-capable clock input and IFF(2) with PLL XC7Z007S N/A 3.03/–0.19 3.64/–0.19 N/A ns XC7Z012S N/A 3.15/–0.20 3.76/–0.20 N/A ns XC7Z014S N/A 3.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Additional Package Parameter Guidelines The parameters in this section provide the necessary values for calculating timing budgets for PL clock transmitter and receiver data-valid windows.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) GTP Transceiver Specifications (Only available in the XC7Z012S and XC7Z015) GTP Transceiver DC Input and Output Levels Table 85 summarizes the DC output specifications of the GTP transceivers in the XC7Z012S and XC7Z015. Consult the 7 Series FPGAs GTP Transceiver User Guide (UG482) for further details.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 86 summarizes the DC specifications of the clock input of the GTP transceiver. Consult the 7 Series FPGAs GTP Transceiver User Guide (UG482) for further details.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 90: GTP Transceiver PLL/Lock Time Adaptation Symbol TLOCK TDLOCK Description All Speed Grades Conditions Initial PLL lock Clock recovery phase acquisition and adaptation time. After the PLL is locked to the reference clock, this is the time it takes to lock the clock data recovery (CDR) to the data present at the input. Units Min Typ Max – – 1 ms – 50,000 2.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 92: GTP Transceiver Transmitter Switching Characteristics Symbol Description FGTPTX Serial data rate range TRTX TX rise time TFTX TX fall time Condition Min Typ Max Units 0.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 93: GTP Transceiver Receiver Switching Characteristics Symbol Description RX oversampler not enabled Min Typ Max Units 0.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) GTP Transceiver Protocol Jitter Characteristics For Table 94 through Table 98, the 7 Series FPGAs GTP Transceiver User Guide (UG482) contains recommended settings for optimal usage of protocol specific characteristics. Table 94: Gigabit Ethernet Protocol Characteristics Description Line Rate (Mb/s) Min Max Units 1250 – 0.24 UI 1250 0.749 – UI Line Rate (Mb/s) Min Max Units 3125 – 0.35 UI 3125 0.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 98: CPRI Protocol Characteristics Description Line Rate (Mb/s) Min Max Units 614.4 – 0.35 UI 1228.8 – 0.35 UI 2457.6 – 0.35 UI 3072.0 – 0.35 UI 4915.2 – 0.3 UI 6144.0 – 0.3 UI 614.4 0.65 – UI 1228.8 0.65 – UI 2457.6 0.65 – UI 3072.0 0.65 – UI 4915.2(1) 0.60 – UI 6144.0(1) 0.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) XADC Specifications Table 100: XADC Specifications Parameter Symbol Comments/Conditions Min Typ Max Units VCCADC = 1.8V ± 5%, VREFP = 1.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Table 100: XADC Specifications (Cont’d) Parameter Symbol Comments/Conditions Min Typ Max Units 1.20 1.25 1.30 V Ground VREFP pin to AGND, –40°C ≤ Tj ≤ 100°C 1.2375 1.25 1.2625 V Ground VREFP pin to AGND, –55°C ≤ Tj < –40°C; 100°C < Tj ≤ 125°C 1.225 1.25 1.275 V XADC Reference(5) External Reference VREFP On-Chip Reference Externally supplied reference voltage Notes: 1. 2. 3. 4. 5.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) eFUSE Programming Conditions Table 102 lists the programming conditions specifically for eFUSE. For more information, see the 7 Series FPGA Configuration User Guide (UG470). Table 102: eFUSE Programming Conditions(1) Symbol Description Min Typ Max Units IPLFS PL VCCAUX supply current – – 115 mA IPSFS PS VCCPAUX supply current – – 115 mA tj Temperature range 15 – 125 °C Notes: 1.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Date Version Description of Revisions 02/14/2013 1.4 Corrected TQSPICKD2 minimum equation in Table 34. Updated timing parameter names in Figure 4 and Figure 5 to match those in the accompanying table. 02/19/2013 1.4.1 03/19/2013 1.5 Updated Table 15 and Table 16 to the product status of production for the XC7Z010 devices with -2 and -1 speed specifications. Updated Figure 4 by adding OUT0.
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Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Date Version Description of Revisions 11/19/2014 1.14 Added VCCBRAM to Introduction. Replaced -1L speed grade with -1LI and removed 1.0V row for VCCINT and VCCBRAM in Table 2. Updated the AC Switching Characteristics based upon Vivado 2014.4. Updated Vivado software version in Table 14. In Table 15, moved -1LI speed grade for XC7Z010, XC7Z015, and XC7Z020 devices from Advance to Production.