Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 10
DC Input and Output Levels
Values for V
IL
and V
IH
are recommended input voltages. Values for I
OL
and I
OH
are guaranteed over the recommended
operating conditions at the V
OL
and V
OH
test points. Only selected standards are tested. These are chosen to ensure that all
standards meet their specifications. The selected standards are tested at a minimum V
CCO
with the respective V
OL
and V
OH
voltage levels shown. Other standards are sample tested.
PS I/O Levels
Table 8: PS DC Input and Output Levels
(1)
Bank
I/O
Standard
V
IL
V
IH
V
OL
V
OH
I
OL
I
OH
V, Min V, Max V, Min V, Max V, Max V, Min mA mA
MIO LVCMOS18 –0.300 35% V
CCO_MIO
65% V
CCO_MIO
V
CCO_MIO
+ 0.300 0.450 V
CCO_MIO
– 0.450 8 –8
MIO LVCMOS25 –0.300 0.700 1.700 V
CCO_MIO
+ 0.300 0.400 V
CCO_MIO
– 0.400 8 –8
MIO LVCMOS33 –0.300 0.800 2.000 3.450 0.400 V
CCO_MIO
– 0.400 8 –8
MIO HSTL_I_18 –0.300 V
PREF
– 0.100 V
PREF
+0.100 V
CCO_MIO
+ 0.300 0.400 V
CCO_MIO
– 0.400 8 –8
DDR SSTL18_I –0.300 V
PREF
– 0.125 V
PREF
+0.125 V
CCO_DDR
+0.300 V
CCO_DDR
/2–0.470 V
CCO_DDR
/2 + 0.470 8 –8
DDR SSTL15 –0.300 V
PREF
– 0.100 V
PREF
+0.100 V
CCO_DDR
+0.300 V
CCO_DDR
/2–0.175 V
CCO_DDR
/2 + 0.175 13.0 –13.0
DDR SSTL135 –0.300 V
PREF
– 0.090 V
PREF
+0.090 V
CCO_DDR
+0.300 V
CCO_DDR
/2–0.150 V
CCO_DDR
/2 + 0.150 13.0 –13.0
DDR HSUL_12 –0.300 V
PREF
– 0.130 V
PREF
+0.130 V
CCO_DDR
+ 0.300 20% V
CCO_DDR
80% V
CCO_DDR
0.1 –0.1
Notes:
1. Tested according to relevant specifications.
Table 9: PS Complementary Differential DC Input and Output Levels
Bank I/O Standard
V
ICM
(1)
V
ID
(2)
V
OL
(3)
V
OH
(4)
I
OL
I
OH
V, Min V,Typ V, Max V,Min V, Max V, Max V, Min mA, Max mA, Min
DDR DIFF_HSUL_12 0.300 0.600 0.850 0.100 – 20% V
CCO
80% V
CCO
0.100 –0.100
DDR DIFF_SSTL135 0.300 0.675 1.000 0.100 – (V
CCO_DDR
/2) – 0.150 (V
CCO_DDR
/2) + 0.150 13.0 –13.0
DDR DIFF_SSTL15 0.300 0.750 1.125 0.100 – (V
CCO_DDR
/2) – 0.175 (V
CCO_DDR
/2) + 0.175 13.0 –13.0
DDR DIFF_SSTL18_I 0.300 0.900 1.425 0.100 – (V
CCO_DDR
/2) – 0.470 (V
CCO_DDR
/2) + 0.470 8.00 –8.00
Notes:
1. V
ICM
is the input common mode voltage.
2. V
ID
is the input differential voltage (Q–Q).
3. V
OL
is the single-ended low-output voltage.
4. V
OH
is the single-ended high-output voltage.