Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 11
PL I/O Levels
Table 10: SelectIO DC Input and Output Levels
(1)(2)
I/O Standard
V
IL
V
IH
V
OL
V
OH
I
OL
I
OH
V, Min V, Max V, Min V, Max V, Max V, Min mA mA
HSTL_I –0.300 V
REF
– 0.100 V
REF
+ 0.100 V
CCO
+ 0.300 0.400 V
CCO
– 0.400 8.00 –8.00
HSTL_I_18 –0.300 V
REF
– 0.100 V
REF
+ 0.100 V
CCO
+ 0.300 0.400 V
CCO
– 0.400 8.00 –8.00
HSTL_II –0.300 V
REF
– 0.100 V
REF
+ 0.100 V
CCO
+ 0.300 0.400 V
CCO
– 0.400 16.00 –16.00
HSTL_II_18 –0.300 V
REF
– 0.100 V
REF
+ 0.100 V
CCO
+ 0.300 0.400 V
CCO
– 0.400 16.00 –16.00
HSUL_12 –0.300 V
REF
– 0.130 V
REF
+ 0.130 V
CCO
+0.300 20%V
CCO
80% V
CCO
0.10 –0.10
LVCMOS12 –0.300 35% V
CCO
65% V
CCO
V
CCO
+ 0.300 0.400 V
CCO
–0.400 Note 3 Note 3
LVCMOS15 –0.300 35% V
CCO
65% V
CCO
V
CCO
+0.300 25%V
CCO
75% V
CCO
Note 4 Note 4
LVCMOS18 –0.300 35% V
CCO
65% V
CCO
V
CCO
+ 0.300 0.450 V
CCO
–0.450 Note 5 Note 5
LVCMOS25 –0.300 0.7 1.700 V
CCO
+ 0.300 0.400 V
CCO
–0.400 Note 4 Note 4
LVCMOS33 –0.300 0.8 2.000 3.450 0.400 V
CCO
–0.400 Note 4 Note 4
LVTTL –0.300 0.8 2.000 3.450 0.400 2.400 Note 5 Note 5
MOBILE_DDR –0.300 20% V
CCO
80% V
CCO
V
CCO
+0.300 10%V
CCO
90% V
CCO
0.10 –0.10
PCI33_3 –0.400 30% V
CCO
50% V
CCO
V
CCO
+0.500 10%V
CCO
90% V
CCO
1.50 –0.50
SSTL135 –0.300 V
REF
– 0.090 V
REF
+ 0.090 V
CCO
+0.300 V
CCO
/2 – 0.150 V
CCO
/2 + 0.150 13.00 –13.00
SSTL135_R –0.300 V
REF
– 0.090 V
REF
+ 0.090 V
CCO
+0.300 V
CCO
/2 – 0.150 V
CCO
/2 + 0.150 8.90 –8.90
SSTL15 –0.300 V
REF
– 0.100 V
REF
+ 0.100 V
CCO
+0.300 V
CCO
/2 – 0.175 V
CCO
/2 + 0.175 13.00 –13.00
SSTL15_R –0.300 V
REF
– 0.100 V
REF
+ 0.100 V
CCO
+0.300 V
CCO
/2 – 0.175 V
CCO
/2 + 0.175 8.90 –8.90
SSTL18_I –0.300 V
REF
– 0.125 V
REF
+ 0.125 V
CCO
+0.300 V
CCO
/2 – 0.470 V
CCO
/2 + 0.470 8.00 –8.00
SSTL18_II –0.300 V
REF
– 0.125 V
REF
+ 0.125 V
CCO
+0.300 V
CCO
/2 – 0.600 V
CCO
/2 + 0.600 13.40 –13.40
Notes:
1. Tested according to relevant specifications.
2. 3.3V and 2.5V standards are only supported in HR I/O banks.
3. Supported drive strengths of 4, 8, or 12 mA in HR I/O banks.
4. Supported drive strengths of 4, 8, 12, or 16 mA in HR I/O banks.
5. Supported drive strengths of 4, 8, 12, 16, or 24 mA in HR I/O banks.
6. For detailed interface specific DC voltage levels, see the 7 Series FPGAs SelectIO Resources User Guide (UG471
).
Table 11: Differential SelectIO DC Input and Output Levels
I/O Standard
V
ICM
(1)
V
ID
(2)
V
OCM
(3)
V
OD
(4)
V, Min V, Typ V, Max V, Min V, Typ V, Max V, Min V, Typ V, Max V, Min V, Typ V, Max
BLVDS_25 0.300 1.200 1.425 0.100 – – – 1.250 – Note 5
MINI_LVDS_25 0.300 1.200 V
CCAUX
0.200 0.400 0.600 1.000 1.200 1.400 0.300 0.450 0.600
PPDS_25 0.200 0.900 V
CCAUX
0.100 0.250 0.400 0.500 0.950 1.400 0.100 0.250 0.400
RSDS_25 0.300 0.900 1.500 0.100 0.350 0.600 1.000 1.200 1.400 0.100 0.350 0.600
TMDS_33 2.700 2.965 3.230 0.150 0.675 1.200 V
CCO
–0.405 V
CCO
–0.300 V
CCO
–0.190 0.400 0.600 0.800
Notes:
1. V
ICM
is the input common mode voltage.
2. V
ID
is the input differential voltage (Q–Q).
3. V
OCM
is the output common mode voltage.
4. V
OD
is the output differential voltage (Q–Q).
5. V
OD
for BLVDS will vary significantly depending on topology and loading.
6. LVDS_25 is specified in Table 13.