Datasheet
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 12
LVDS DC Specifications (LVDS_25)
Table 12: Complementary Differential SelectIO DC Input and Output Levels
I/O Standard
V
ICM
(1)
V
ID
(2)
V
OL
(3)
V
OH
(4)
I
OL
I
OH
V, Min V,Typ V, Max V,Min V, Max V, Max V, Min mA, Max mA, Min
DIFF_HSTL_I 0.300 0.750 1.125 0.100 – 0.400 V
CCO
–0.400 8.00 –8.00
DIFF_HSTL_I_18 0.300 0.900 1.425 0.100 – 0.400 V
CCO
–0.400 8.00 –8.00
DIFF_HSTL_II 0.300 0.750 1.125 0.100 – 0.400 V
CCO
–0.400 16.00 –16.00
DIFF_HSTL_II_18 0.300 0.900 1.425 0.100 – 0.400 V
CCO
–0.400 16.00 –16.00
DIFF_HSUL_12 0.300 0.600 0.850 0.100 – 20% V
CCO
80% V
CCO
0.100 –0.100
DIFF_MOBILE_DDR 0.300 0.900 1.425 0.100 – 10% V
CCO
90% V
CCO
0.100 –0.100
DIFF_SSTL135 0.300 0.675 1.000 0.100 – (V
CCO
/2) – 0.150 (V
CCO
/2) + 0.150 13.0 –13.0
DIFF_SSTL135_R 0.300 0.675 1.000 0.100 – (V
CCO
/2) – 0.150 (V
CCO
/2) + 0.150 8.9 –8.9
DIFF_SSTL15 0.300 0.750 1.125 0.100 – (V
CCO
/2) – 0.175 (V
CCO
/2) + 0.175 13.0 –13.0
DIFF_SSTL15_R 0.300 0.750 1.125 0.100 – (V
CCO
/2) – 0.175 (V
CCO
/2) + 0.175 8.9 –8.9
DIFF_SSTL18_I 0.300 0.900 1.425 0.100 – (V
CCO
/2) – 0.470 (V
CCO
/2) + 0.470 8.00 –8.00
DIFF_SSTL18_II 0.300 0.900 1.425 0.100 – (V
CCO
/2) – 0.600 (V
CCO
/2) + 0.600 13.4 –13.4
Notes:
1. V
ICM
is the input common mode voltage.
2. V
ID
is the input differential voltage (Q–Q).
3. V
OL
is the single-ended low-output voltage.
4. V
OH
is the single-ended high-output voltage.
Table 13: LVDS_25 DC Specifications
(1)
Symbol DC Parameter Conditions Min Typ Max Units
V
CCO
Supply voltage 2.375 2.5 2.625 V
V
OH
Output High voltage for Q and Q R
T
= 100Ω across Q and Q signals – – 1.675 V
V
OL
Output Low voltage for Q and Q R
T
= 100Ω across Q and Q signals 0.700 – – V
V
ODIFF
Differential output voltage:
(Q – Q
), Q = High
(Q
–Q), Q=High
R
T
= 100Ω across Q and Q signals 247 350 600 mV
V
OCM
Output common-mode voltage R
T
= 100Ω across Q and Q signals 1.00 1.25 1.425 V
V
IDIFF
Differential input voltage:
(Q – Q
), Q = High
(Q
–Q), Q=High
100 350 600 mV
V
ICM
Input common-mode voltage 0.3 1.2 1.500 V
Notes:
1. Differential inputs for LVDS_25 can be placed in banks with V
CCO
levels that are different from the required level for outputs. Consult the
7 Series FPGAs SelectIO Resources User Guide (UG471
) for more information.