Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 16
PS Switching Characteristics
Clocks
Resets
The PS_POR_B deassertion must meet the following requirements to avoid coinciding with the secure lockdown window.
Figure 1 shows the timing relationship between PS_POR_B and the last power supply ramp (V
CCINT
, V
CCBRAM
, V
CCAUX
, or V
CCO
in bank 0). T
SLW
minimum and maximum parameters define the beginning and end, respectively, of the secure lockdown
window relative to the last PL power supply reaching 250 mV. The PS_POR_B must not be deasserted within the secure
lockdown window.
Table 20: System Reference Clock Input Requirements
Symbol Description Min Typ Max Units
T
JTPSCLK
PS_CLK RMS clock jitter tolerance – – ±0.5 %
T
DCPSCLK
PS_CLK duty cycle 40 – 60 %
T
RFPSCLK
PS_CLK rise and fall time – – 6 ns
F
PSCLK
PS_CLK frequency 30 – 60 MHz
Table 21: PS PLL Switching Characteristics
Symbol Description
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
T
LOCK_PSPLL
PLL maximum lock time 60 60 60 60 µs
F
PSPLL_MAX
PLL maximum output frequency 2000 1800 1600 1600 MHz
F
PSPLL_MIN
PLL minimum output frequency 780 780 780 780 MHz
Table 22: PS Reset Assertion Timing Requirements
Symbol Description Min Typ Max Units
T
PSPOR
Required PS_POR_B assertion time
(1)
100 – – µs
T
PSRST
Required PS_SRST_B assertion time 3 – – PS_CLK Clock Cycles
Notes:
1. PS_POR_B needs to be asserted Low until T
PSPOR
after PS supply voltages reach minimum levels.
X-Ref Target - Figure 1
Figure 1: PS_POR_B and Power Supply Ramp Timing Requirements
PS_POR_B
Last Ramping PL Supply
Secure Lockdown Window
Do not deassert PS_POR_B
T
SLW(min)
T
SLW(max)
250 mV
DS187_22_022015