Datasheet
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 17
PS Configuration
DDR Memory Interfaces
Table 23: PS Reset/Power Supply Timing Requirements
Symbol Description
PS_CLK Frequency
(MHz)
Min Max Units
T
SLW
(1)
128 KB CRC eFUSE disabled and PLL enabled.
Default configuration
30 12 39 ms
33.33 12 40 ms
60 13 40 ms
128 KB CRC eFUSE disabled and PLL in bypass. 30 –32 13 ms
33.33 –27 13 ms
60 –9 25 ms
128 KB CRC eFUSE enabled and PLL enabled.
(2)
30 –19 9 ms
33.33 –16 12 ms
60 –3 25 ms
128 KB CRC eFUSE enabled and PLL in bypass.
(2)
30 –830 –788 ms
33.33 –746 –705 ms
60 –408 –374 ms
Notes:
1. Valid for power supply ramp times of less than 6 ms. For ramp times longer than 6 ms, see the BootROM Performance section of the
Zynq-7000 All Programmable SoC Technical Reference Manual (UG585
).
2. If any PS and PL power supplies are tied together, observe the PS_POR_B assertion time requirement (T
PSPOR
) in Table 22 and its
accompanying note.
Table 24: Processor Configuration Access Port Switching Characteristics
Symbol Description Min Typ Max Units
F
PCAPCK
Maximum processor configuration access port (PCAP)
frequency
––100 MHz
Table 25: DDR3 Interface Switching Characteristics (1066 Mb/s)
(1)
Symbol Description Min Max Units
T
DQVALID
(2)
Input data valid window 450 – ps
T
DQDS
(3)
Output DQ to DQS skew 131 – ps
T
DQDH
(4)
Output DQS to DQ skew 288 – ps
T
DQSS
Output clock to DQS skew –0.11 0.09 T
CK
T
CACK
(5)
Command/address output setup time with respect to CLK 532 – ps
T
CKCA
(6)
Command/address output hold time with respect to CLK 637 – ps
Notes:
1. Recommended V
CCO_DDR
=1.5V±5%.
2. Measurement is taken from V
REF
to V
REF
.
3. Measurement is taken from either the rising edge of DQ that crosses V
IH
(AC) or the falling edge of DQ that crosses V
IL
(AC) to V
REF
of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses V
IL
(DC) or the falling edge of DQ that crosses V
IH
(DC) to V
REF
of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses V
IH
(AC) or the falling edge of CMD/ADDR that crosses
V
IL
(AC) to V
REF
of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses V
IL
(DC) or the falling edge of CMD/ADDR that crosses
V
IH
(DC) to V
REF
of CLK.