Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 18
Table 26: DDR3 Interface Switching Characteristics (800 Mb/s)
(1)
Symbol Description Min Max Units
T
DQVALID
(2)
Input data valid window 500 – ps
T
DQDS
(3)
Output DQ to DQS skew 232 – ps
T
DQDH
(4)
Output DQS to DQ skew 401 – ps
T
DQSS
Output clock to DQS skew –0.10 0.06 T
CK
T
CACK
(5)
Command/address output setup time with respect to CLK 722 – ps
T
CKCA
(6)
Command/address output hold time with respect to CLK 882 – ps
Notes:
1. Recommended V
CCO_DDR
=1.5V±5%.
2. Measurement is taken from V
REF
to V
REF
.
3. Measurement is taken from either the rising edge of DQ that crosses V
IH
(AC) or the falling edge of DQ that crosses V
IL
(AC) to V
REF
of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses V
IL
(DC) or the falling edge of DQ that crosses V
IH
(DC) to V
REF
of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses V
IH
(AC) or the falling edge of CMD/ADDR that crosses
V
IL
(AC) to V
REF
of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses V
IL
(DC) or the falling edge of CMD/ADDR that crosses
V
IH
(DC) to V
REF
of CLK.
Table 27: DDR3L Interface Switching Characteristics (1066 Mb/s)
(1)
Symbol Description Min Max Units
T
DQVALID
(2)
Input data valid window 450 – ps
T
DQDS
(3)
Output DQ to DQS skew 189 – ps
T
DQDH
(4)
Output DQS to DQ skew 267 – ps
T
DQSS
Output clock to DQS skew –0.13 0.04 T
CK
T
CACK
(5)
Command/address output setup time with respect to CLK 410 – ps
T
CKCA
(6)
Command/address output hold time with respect to CLK 629 – ps
Notes:
1. Recommended V
CCO_DDR
= 1.35V ±5%.
2. Measurement is taken from V
REF
to V
REF
.
3. Measurement is taken from either the rising edge of DQ that crosses V
IH
(AC) or the falling edge of DQ that crosses V
IL
(AC) to V
REF
of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses V
IL
(DC) or the falling edge of DQ that crosses V
IH
(DC) to V
REF
of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses V
IH
(AC) or the falling edge of CMD/ADDR that crosses V
IL
(AC)
to V
REF
of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses V
IL
(DC) or the falling edge of CMD/ADDR that crosses
V
IH
(DC) to V
REF
of CLK.
Table 28: DDR3L Interface Switching Characteristics (800 Mb/s)
(1)
Symbol Description Min Max Units
T
DQVALID
(2)
Input data valid window 500 – ps
T
DQDS
(3)
Output DQ to DQS skew 321 – ps
T
DQDH
(4)
Output DQS to DQ skew 380 – ps
T
DQSS
Output clock to DQS skew –0.12 0.04 T
CK
T
CACK
(5)
Command/address output setup time with respect to CLK 636 – ps