Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 19
T
CKCA
(6)
Command/address output hold time with respect to CLK 853 – ps
Notes:
1. Recommended V
CCO_DDR
= 1.35V ±5%.
2. Measurement is taken from V
REF
to V
REF
.
3. Measurement is taken from either the rising edge of DQ that crosses V
IH
(AC) or the falling edge of DQ that crosses V
IL
(AC) to V
REF
of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses V
IL
(DC) or the falling edge of DQ that crosses V
IH
(DC) to V
REF
of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses V
IH
(AC) or the falling edge of CMD/ADDR that crosses
V
IL
(AC) to V
REF
of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses V
IL
(DC) or the falling edge of CMD/ADDR that crosses
V
IH
(DC) to V
REF
of CLK.
Table 29: LPDDR2 Interface Switching Characteristics (800 Mb/s)
(1)
Symbol Description Min Max Units
T
DQVALID
(2)
Input data valid window 500 – ps
T
DQDS
(3)
Output DQ to DQS skew 196 – ps
T
DQDH
(4)
Output DQS to DQ skew 328 – ps
T
DQSS
Output clock to DQS skew 0.90 1.06 T
CK
T
CACK
(5)
Command/address output setup time with respect to CLK 202 – ps
T
CKCA
(6)
Command/address output hold time with respect to CLK 353 – ps
Notes:
1. Recommended V
CCO_DDR
=1.2V±5%.
2. Measurement is taken from V
REF
to V
REF
.
3. Measurement is taken from either the rising edge of DQ that crosses V
IH
(AC) or the falling edge of DQ that crosses V
IL
(AC) to V
REF
of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses V
IL
(DC) or the falling edge of DQ that crosses V
IH
(DC) to V
REF
of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses V
IH
(AC) or the falling edge of CMD/ADDR that crosses V
IL
(AC)
to V
REF
of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses V
IL
(DC) or the falling edge of CMD/ADDR that crosses
V
IH
(DC) to V
REF
of CLK.
Table 30: LPDDR2 Interface Switching Characteristics (400 Mb/s)
(1)
Symbol Description Min Max Units
T
DQVALID
(2)
Input data valid window 500 – ps
T
DQDS
(3)
Output DQ to DQS skew 664 – ps
T
DQDH
(4)
Output DQS to DQ skew 766 – ps
T
DQSS
Output clock to DQS skew 0.90 1.06 T
CK
T
CACK
(5)
Command/address output setup time with respect to CLK 731 – ps
T
CKCA
(6)
Command/address output hold time with respect to CLK 907 – ps
Notes:
1. Recommended V
CCO_DDR
=1.2V±5%.
2. Measurement is taken from V
REF
to V
REF
.
3. Measurement is taken from either the rising edge of DQ that crosses V
IH
(AC) or the falling edge of DQ that crosses V
IL
(AC) to V
REF
of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses V
IL
(DC) or the falling edge of DQ that crosses V
IH
(DC) to V
REF
of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses V
IH
(AC) or the falling edge of CMD/ADDR that crosses V
IL
(AC)
to V
REF
of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses V
IL
(DC) or the falling edge of CMD/ADDR that crosses
V
IH
(DC) to V
REF
of CLK.
Table 28: DDR3L Interface Switching Characteristics (800 Mb/s)
(1)
(Cont’d)
Symbol Description Min Max Units