Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 20
Table 31: DDR2 Interface Switching Characteristics (800 Mb/s)
(1)
Symbol Description Min Max Units
T
DQVALID
(2)
Input data valid window 500 – ps
T
DQDS
(3)
Output DQ to DQS skew 147 – ps
T
DQDH
(4)
Output DQS to DQ skew 376 – ps
T
DQSS
Output clock to DQS skew –0.07 0.08 T
CK
T
CACK
(5)
Command/address output setup time with respect to CLK 732 – ps
T
CKCA
(6)
Command/address output hold time with respect to CLK 938 – ps
Notes:
1. Recommended V
CCO_DDR
=1.8V±5%.
2. Measurement is taken from V
REF
to V
REF
.
3. Measurement is taken from either the rising edge of DQ that crosses V
IH
(AC) or the falling edge of DQ that crosses V
IL
(AC) to V
REF
of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses V
IL
(DC) or the falling edge of DQ that crosses V
IH
(DC) to V
REF
of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses V
IH
(AC) or the falling edge of CMD/ADDR that crosses
V
IL
(AC) to V
REF
of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses V
IL
(DC) or the falling edge of CMD/ADDR that crosses
V
IH
(DC) to V
REF
of CLK.
Table 32: DDR2 Interface Switching Characteristics (400 Mb/s)
(1)
Symbol Description Min Max Units
T
DQVALID
(2)
Input data valid window 500 – ps
T
DQDS
(3)
Output DQ to DQS skew 385 – ps
T
DQDH
(4)
Output DQS to DQ skew 662 – ps
T
DQSS
Output clock to DQS skew –0.11 0.06 T
CK
T
CACK
(5)
Command/address output setup time with respect to CLK 1760 – ps
T
CKCA
(6)
Command/address output hold time with respect to CLK 1739 – ps
Notes:
1. Recommended V
CCO_DDR
=1.8V±5%.
2. Measurement is taken from V
REF
to V
REF
.
3. Measurement is taken from either the rising edge of DQ that crosses V
IH
(AC) or the falling edge of DQ that crosses V
IL
(AC) to V
REF
of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses V
IL
(DC) or the falling edge of DQ that crosses V
IH
(DC) to V
REF
of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses V
IH
(AC) or the falling edge of CMD/ADDR that crosses
V
IL
(AC) to V
REF
of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses V
IL
(DC) or the falling edge of CMD/ADDR that crosses
V
IH
(DC) to V
REF
of CLK.