Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 21
X-Ref Target - Figure 2
Figure 2: DDR Output Timing Diagram
X-Ref Target - Figure 3
Figure 3: DDR Input Timing Diagram
Write NOP NOP NOP NOP
Bank, Col n
D0 D1 D3
T
DQDH
T
DQDS
T
DQDH
T
DQDS
T
DQSS
T
CKCA
T
CACK
T
CKCA
T
CACK
DS187_01_012213
CLK
CLK
Command
Address
DQS
DQS
DQ
D2
D0 D1 D2 D3
T
DQVALID
CLK
CLK
DQS
DQS
DQ
DS187_02_012213