Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 22
Static Memory Controller
Table 33: SMC Interface Delay Characteristics
(1)(2)
Symbol Description Min Max Units
T
NANDDOUT
NAND_IO output delay from last register to pad 4.12 6.45 ns
T
NANDALE
NAND_ALE output delay from last register to pad 5.08 6.33 ns
T
NANDCLE
NAND_CLE output delay from last register to pad 4.87 6.40 ns
T
NANDWE
NAND_WE_B output delay from last register to pad 4.69 5.89 ns
T
NANDRE
NAND_RE_B output delay from last register to pad 5.12 6.44 ns
T
NANDCE
NAND_CE_B output delay from last register to pad 4.68 5.89 ns
T
NANDDIN
NAND_IO setup time and input delay from pad to first register 1.48 3.09 ns
T
NANDBUSY
NAND_BUSY setup time and input delay from pad to first register 2.48 3.33 ns
T
SRAMA
SRAM_A output delay from last register to pad 3.94 5.73 ns
T
SRAMDOUT
SRAM_DQ output delay from last register to pad 4.66 6.45 ns
T
SRAMCE
SRAM_CE output delay from last register to pad 4.57 5.95 ns
T
SRAMOE
SRAM_OE_B output delay from last register to pad 4.79 6.13 ns
T
SRAMBLS
SRAM_BLS_B output delay from last register to pad 5.25 6.74 ns
T
SRAMWE
SRAM_WE_B output delay from last register to pad 5.12 6.48 ns
T
SRAMDIN
SRAM_DQ setup time and input delay from pad to first register 1.93 3.05 ns
T
SRAMWAIT
SRAM_WAIT setup time and input delay from pad to first register 2.26 3.15 ns
F
SMC_REF_CLK
SMC reference clock frequency – 100 MHz
Notes:
1. All parameters do not include the package flight time and register controlled delays.
2. Refer to the ARM® PrimeCell® Static Memory Controller (PL350 series) Technical Reference Manual for more SMC timing details.