Datasheet
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 23
Quad-SPI Interfaces
Table 34: Quad-SPI Interface Switching Characteristics
Symbol Description
Load
Conditions
Min Max Units
Feedback Clock Enabled
T
DCQSPICLK1
Quad-SPI clock duty cycle All
(1)(2)
44 56 %
T
QSPICKO1
Data and slave select output delay
15 pF
(1)
–0.10
(3)
2.30
ns
30 pF
(2)
–1.00 3.80
T
QSPIDCK1
Input data setup time
15 pF
(1)
2.00 –
ns
30 pF
(2)
3.30 –
T
QSPICKD1
Input data hold time
15 pF
(1)
1.30 –
ns
30 pF
(2)
1.50 –
T
QSPISSCLK1
Slave select asserted to next clock edge All
(1)(2)
1–F
QSPI_REF_CLK
cycle
T
QSPICLKSS1
Clock edge to slave select deasserted All
(1)(2)
1–F
QSPI_REF_CLK
cycle
F
QSPICLK1
Quad-SPI device clock frequency
15 pF
(1)
– 100
(4)
MHz
30 pF
(2)
–70
(4)
Feedback Clock Disabled
T
DCQSPICLK2
Quad-SPI clock duty cycle All
(1)(2)
44 56 %
T
QSPICKO2
Data and slave select output delay 15 pF
(1)
–0.10 3.80 ns
30 pF
(2)
–1.00 3.80 ns
T
QSPIDCK2
Input data setup time All
(1)(2)
6–ns
T
QSPICKD2
Input data hold time All
(1)(2)
12.5 – ns
T
QSPISSCLK2
Slave select asserted to next clock edge All
(1)(2)
1–F
QSPI_REF_CLK
cycle
T
QSPICLKSS2
Clock edge to slave select deasserted All
(1)(2)
1–F
QSPI_REF_CLK
cycle
F
QSPICLK2
Quad-SPI device clock frequency All
(1)(2)
–40MHz
Feedback Clock Enabled or Disabled
F
QSPI_REF_CLK
Quad-SPI reference clock frequency All
(1)(2)
–200MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads, feedback clock pin has no load. Quad-SPI single slave select
4-bit I/O mode.
2. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 30 pF loads in 4-bit stacked I/O configuration, feedback clock pin has no
load. Quad-SPI single slave select 4-bit I/O mode.
3. The T
QSPICKO1
is an effective value. Use it to compute the available memory device input setup and hold timing budgets based on the given
device clock-out duty-cycle limits.
4. Requires appropriate component selection/board design.