Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 24
X-Ref Target - Figure 4
Figure 4: Quad-SPI Interface (Feedback Clock Enabled) Timing Diagram
X-Ref Target - Figure 5
Figure 5: Quad-SPI Interface (Feedback Clock Disabled) Timing Diagram
QSPI{1,0}_SS_B
QSPI_SCLK_OUT
CPOL = 0
QSPI{1,0}_IO_[3,0]
QSPI_SCLK_OUT
CPOL = 1
DS187_03_110515
T
QSPICKO1
T
QSPISSCLK1
T
QSPISSCLK1
T
QSPICLKSS1
T
QSPICLKSS1
T
QSPIDCK1
T
QSPICKD1
OUT1OUT0 INn-2 INn-1 INn
OUT0 OUT1 INn-1
QSPI{1,0}_SS_B
QSPI_SCLK_OUT
(CPOL = 0)
QSPI_SCLK_OUT
(CPOL = 1)
QSPI{0,1}_IO_[3:0]
T
QSPICKD2
T
QSPIDCK2
T
QSPICKO2
T
QSPICLKSS2
T
QSPISSCLK2
T
QSPICLKSS2
T
QSPISSCLK2
INn
DS187_04_110515