Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 25
ULPI Interfaces
Table 35: ULPI Interface Clock Receiving Mode Switching Characteristics
(1)(2)
Symbol Description Min Typ Max Units
T
ULPIDCK
Input setup to ULPI clock, all inputs 3.00 – – ns
T
ULPICKD
Input hold to ULPI clock, all inputs 1.00 – – ns
T
ULPICKO
ULPI clock to output valid, all outputs 1.70 – 8.86 ns
F
ULPICLK
ULPI device clock frequency – 60 – MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads, 60 MHz device clock frequency.
2. All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional external clock jitter.
X-Ref Target - Figure 6
Figure 6: ULPI Interface Timing Diagram
T
ULPICKO
T
ULPICKO
T
ULPICKD
T
ULPIDCK
T
ULPICKD
T
ULPIDCK
USB{0,1}_ULPI_CLK
USB{0,1}_ULPI_DATA[7:0] (Input)
USB{0,1}_ULPI_DIR,
USB{0,1}_ULPI_NXT
USB{0,1}_ULPI_STP
USB{0,1}_ULPI_DATA[7:0] (Output)
DS187_05_021013