Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 26
RGMII and MDIO Interfaces
Table 36: RGMII and MDIO Interface Switching Characteristics
(1)(2)(3)
Symbol Description Min Typ Max Units
T
DCGETXCLK
Transmit clock duty cycle 45 – 55 %
T
GEMTXCKO
RGMII_TX_D[3:0], RGMII_TX_CTL output clock to out time –0.50 – 0.50 ns
T
GEMRXDCK
RGMII_RX_D[3:0], RGMII_RX_CTL input setup time 0.80 – – ns
T
GEMRXCKD
RGMII_RX_D[3:0], RGMII_RX_CTL input hold time 0.80 – – ns
T
MDIOCLK
MDC output clock period 400 – – ns
T
MDIOCKH
MDC clock High time 160 – – ns
T
MDIOCKL
MDC clock Low time 160 – – ns
T
MDIODCK
MDIO input data setup time 80 – – ns
T
MDIOCKD
MDIO input data hold time 0 – – ns
T
MDIOCKO
MDIO data output delay –20 – 170 ns
F
GETXCLK
RGMII_TX_CLK transmit clock frequency – 125 – MHz
F
GERXCLK
RGMII_RX_CLK receive clock frequency – 125 – MHz
F
ENET_REF_CLK
Ethernet reference clock frequency – 125 – MHz
Notes:
1. Test conditions: LVCMOS25, fast slew rate, 8 mA drive strength, 15 pF loads. Values in this table are specified during 1000 Mb/s operation.
2. LVCMOS25 slow slew rate and LVCMOS33 are not supported.
3. All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional external clock jitter.
X-Ref Target - Figure 7
Figure 7: RGMII Interface Timing Diagram
RGMII_TX_CLK
MDIO_CLK
RGMII_RX_CLK
T
GEMTXCKO
T
MDIOCKH
T
MDIOCLK
T
MDIOCKL
T
GEMRXCKD
RGMII_TX_D[3:0]
RGMII_TX_CTL
RGMII_RX_D[3:0]
RGMII_RX_CTL
T
GEMRXDCK
T
MDIOCKD
MDIO_IO (Input)
T
MDIODCK
DS187_06_021013
MDIO_IO (Output)
T
MDIOCKO