Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 27
SD/SDIO Interfaces
Table 37: SD/SDIO Interface High Speed Mode Switching Characteristics
(1)
Symbol Description Min Typ Max Units
T
DCSDHSCLK
SD device clock duty cycle – 50 – %
T
SDHSCKO
Clock to output delay, all outputs 2.00 – 12.00 ns
T
SDHSDCK
Input setup time, all inputs 3.00 – – ns
T
SDHSCKD
Input hold time, all inputs 1.05 – – ns
F
SD_REF_CLK
SD reference clock frequency – – 125 MHz
F
SDHSCLK
High speed mode SD device clock frequency 0 – 50 MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
X-Ref Target - Figure 8
Figure 8: SD/SDIO Interface High Speed Mode Timing Diagram
Table 38: SD/SDIO Interface Switching Characteristics
(1)
Symbol Description Min Typ Max Units
T
DCSDSCLK
SD device clock duty cycle – 50 – %
T
SDSCKO
Clock to output delay, all outputs 2.00 – 12.00 ns
T
SDSDCK
Input setup time, all inputs 4.00 – – ns
T
SDSCKD
Input hold time, all inputs 3.00 – – ns
F
SD_REF_CLK
SD reference clock frequency – – 125 MHz
F
SDIDCLK
Clock frequency in identification mode – – 400 KHz
F
SDSCLK
Standard mode SD device clock frequency 0 – 25 MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
X-Ref Target - Figure 9
Figure 9: SD/SDIO Interface Standard Mode Timing Diagram
T
SDHSCKO
T
SDHSCKD
T
SDHSDCK
SD{0,1}_CLK
SD{0,1}_DATA[3:0],
SD{0,1}_CMD (input)
SD{0,1}_DATA[3:0],
SD{0,1}_CMD (output)
DS187_07_021013
DS191_108_030113
T
SDSCKO
T
SDSCKD
T
SDSDCK
SD{0,1}_CLK
SD{0,1}_DATA[3:0],
SD{0,1}_CMD (input)
SD{0,1}_DATA[3:0],
SD{0,1}_CMD (output)