Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 29
SPI Interfaces
Table 41: SPI Master Mode Interface Switching Characteristics
(1)
Symbol Description Min Typ Max Units
T
DCMSPICLK
SPI master mode clock duty cycle – 50 – %
T
MSPIDCK
Input setup time for SPI{0,1}_MISO 2.00 – – ns
T
MSPICKD
Input hold time for SPI{0,1}_MISO 8.20 – – ns
T
MSPICKO
Output delay for SPI{0,1}_MOSI and SPI{0,1}_SS –3.10 – 3.90 ns
T
MSPISSCLK
Slave select asserted to first active clock edge 1 – – F
SPI_REF_CLK
cycles
T
MSPICLKSS
Last active clock edge to slave select deasserted 0.5 – – F
SPI_REF_CLK
cycles
F
MSPICLK
SPI master mode device clock frequency – – 50.00 MHz
F
SPI_REF_CLK
SPI reference clock frequency – – 200.00 MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
X-Ref Target - Figure 12
Figure 12: SPI Master (CPHA = 0) Interface Timing Diagram
X-Ref Target - Figure 13
Figure 13: SPI Master (CPHA = 1) Interface Timing Diagram
Dn Dn–1 Dn–2 Dn–3 D0
Dn Dn–1 Dn–2
T
MSPICKD
T
MSPIDCK
T
MSPICKO
T
MSPICLKSS
T
MSPISSCLK
SPI{0,1}_SS
SPI{0,1}_CLK (CPOL=0)
SPI{0,1}_CLK (CPOL=1)
SPI{0,1}_MOSI
SPI{0,1}_MISO
DS187_10_021013
Dn Dn–1 Dn–2 Dn–3 D0
Dn Dn–1 Dn–2 Dn–3 D0
T
MSPICKD
T
MSPIDCK
T
MSPICKO
T
MSPICLKSS
T
MSPISSCLK
SPI{0,1}_SS
SPI{0,1}_CLK (CPOL=0)
SPI{0,1}_CLK (CPOL=1)
SPI{0,1}_MOSI
SPI{0,1}_MISO
DS187_11_021013