Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 30
Table 42: SPI Slave Mode Interface Switching Characteristics
(1)(2)
Symbol Description Min Max Units
T
SSPIDCK
Input setup time for SPI{0,1}_MOSI and SPI{0,1}_SS 1 – F
SPI_REF_CLK
cycles
T
SSPICKD
Input hold time for SPI{0,1}_MOSI and SPI{0,1}_SS 1 – F
SPI_REF_CLK
cycles
T
SSPICKO
Output delay for SPI{0,1}_MISO 0 2.6 F
SPI_REF_CLK
cycles
T
SSPISSCLK
Slave select asserted to first active clock edge 1 – F
SPI_REF_CLK
cycles
T
SSPICLKSS
Last active clock edge to slave select deasserted 1 – F
SPI_REF_CLK
cycles
F
SSPICLK
SPI slave mode device clock frequency – 25 MHz
F
SPI_REF_CLK
SPI reference clock frequency – 200 MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
2. All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional external clock jitter.
X-Ref Target - Figure 14
Figure 14: SPI Slave (CPHA = 0) Interface Timing Diagram
X-Ref Target - Figure 15
Figure 15: SPI Slave (CPHA = 1) Interface Timing Diagram
Dn Dn–1 Dn–2 Dn–3 D0
Dn Dn–1 Dn–2 Dn–3 D0
T
SSPICKO
T
SSPICKD
T
SSPIDCK
T
SSPICLKSS
T
SSPISSCLK
SPI{0,1}_SS
SPI{0,1}_CLK (CPOL=0)
SPI{0,1}_CLK (CPOL=1)
SPI{0,1}_MOSI
SPI{0,1}_MISO
DS187_12_021013
Dn Dn–1 Dn–2 Dn–3 D0
Dn Dn–1 Dn–2 Dn–3 D0
T
SSPICKO
T
SSPICKD
T
SSPIDCK
T
SSPICLKSS
T
SSPISSCLK
SPI{0,1}_SS
SPI{0,1}_CLK (CPOL=0)
SPI{0,1}_CLK (CPOL=1)
SPI{0,1}_MOSI
SPI{0,1}_MISO
DS187_13_021013