Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 31
CAN Interfaces
PJTAG Interfaces
UART Interfaces
Table 43: CAN Interface Switching Characteristics
(1)
Symbol Description Min Max Units
T
PWCANRX
Minimum receive pulse width 1 – µs
T
PWCANTX
Minimum transmit pulse width 1 – µs
F
CAN_REF_CLK
Internally sourced CAN reference clock frequency – 100 MHz
Externally sourced CAN reference clock frequency – 40 MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
Table 44: PJTAG Interface
(1)(2)
Symbol Description Min Max Units
T
PJTAGDCK
PJTAG input setup time 2.4 – ns
T
PJTAGCKD
PJTAG input hold time 2.0 – ns
T
PJTAGCKO
PJTAG clock to out delay – 12.5 ns
T
PJTAGCLK
PJTAG clock frequency – 20 MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
2. All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional external clock jitter.
X-Ref Target - Figure 16
Figure 16: PJTAG Interface Timing Diagram
Table 45: UART Interface Switching Characteristics
(1)
Symbol Description Min Max Units
BAUD
TXMAX
Maximum transmit baud rate – 1 Mb/s
BAUD
RXMAX
Maximum receive baud rate – 1 Mb/s
F
UART_REF_CLK
UART reference clock frequency – 100 MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
PJTAGCLK
PJTAGTMS, PJTAGTDI
PJTAGTDO
T
PJTAGDCK
T
PJTAGCKD
T
PJTAGCKO
DS187_14_021013