Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 32
GPIO Interfaces
Trace Interface
Triple Timer Counter Interface
Watchdog Timer
Table 46: GPIO Banks Switching Characteristics
(1)
Symbol Description Min Max Units
T
PWGPIOH
Input high pulse width 10 x 1/cpu1x – µs
T
PWGPIOL
Input low pulse width 10 x 1/cpu1x – µs
Notes:
1. Pulse width requirement for interrupt.
X-Ref Target - Figure 17
Figure 17: GPIO Interface Timing Diagram
Table 47: Trace Interface Switching Characteristics
(1)
Symbol Description Min Max Units
T
TCECKO
Trace clock to output delay, all outputs –1.4 1.5 ns
T
DCTCECLK
Trace clock duty cycle 40 60 %
F
TCECLK
Trace clock frequency – 80 MHz
Notes:
1. Test conditions: LVCMOS25, fast slew rate, 8 mA drive strength, 15 pF loads.
Table 48: Triple Timer Counter interface Switching Characteristics
(1)
Symbol Description Min Max Units
T
PWTTCOCLK
Triple timer counter output clock pulse width 2 x 1/cpu1x – ns
F
TTCOCLK
Triple timer counter output clock frequency – cpu1x/4 MHz
T
TTCICLKH
Triple timer counter input clock high pulse width 1.5 x 1/cpu1x – ns
T
TTCICLKL
Triple timer counter input clock low pulse width 1.5 x 1/cpu1x – ns
F
TTCICLK
Triple timer counter input clock frequency – cpu1x/3 MHz
Notes:
1. All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional external clock jitter.
Table 49: Watchdog Timer Switching Characteristics
Symbol Description Min Max Units
F
WDTCLK
(1)
Watchdog timer input clock frequency – 10 MHz
Notes:
1. Applies to external input clock through MIO pin only.
T
PWGPIOL
T
PWGPIOH
GPIO
DS187_15_021013