Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 33
PL Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in the PL. The
numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same
guidelines as the AC Switching Characteristics, page 13.
Table 50: PL Networking Applications Interface Performances
Description
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 8) 680 680 600 600 Mb/s
DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14) 1250 1250 950 950 Mb/s
SDR LVDS receiver (SFI-4.1)
(1)
680 680 600 600 Mb/s
DDR LVDS receiver (SPI-4.2)
(1)
1250 1250 950 950 Mb/s
Notes:
1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate
deterministic performance.
Table 51: Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface
Generator
(1)(2)
Memory Standard
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
4:1 Memory Controllers
DDR3 1066
(3)
800 800 667 Mb/s
DDR3L 800 800 667 N/A Mb/s
DDR2 800 800 667 533 Mb/s
2:1 Memory Controllers
DDR3 800 700 620 620 Mb/s
DDR3L 800 700 620 N/A Mb/s
DDR2 800 700 620 533 Mb/s
LPDDR2 667 667 533 400 Mb/s
Notes:
1. V
REF
tracking is required. For more information, see the Zynq-7000 AP SoC and 7 Series Devices Memory Interface Solutions User
Guide (UG586
).
2. When using the internal V
REF
, the maximum data rate is 800 Mb/s (400 MHz).
3. The maximum PHY rate is 800 Mb/s in bank 13 of the XC7Z015, XC7Z020, XA7Z020, and XQ7Z020 devices.