Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 34
PL Switching Characteristics
IOB Pad Input/Output/3-State
Table 52 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based
on standard), and 3-state delays.
•T
IOPI
is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies
depending on the capability of the SelectIO input buffer.
•T
IOOP
is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies
depending on the capability of the SelectIO output buffer.
•T
IOTP
is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is
disabled. The delay varies depending on the SelectIO capability of the output buffer. In HR I/O banks, the IN_TERM
termination turn-on time is always faster than T
IOTP
when the INTERMDISABLE pin is used.
Table 52: IOB High Range (HR) Switching Characteristics
I/O Standard
T
IOPI
T
IOOP
T
IOTP
Units
Speed Grade Speed Grade Speed Grade
-3 -2
-1C/-1I/
-1LI
-1Q -3 -2
-1C/-1I/
-1LI
-1Q -3 -2
-1C/-1I/
-1LI
-1Q
LVTTL_S4 1.26 1.34 1.41 1.53 3.80 3.93 4.18 4.18 3.82 3.96 4.20 4.20 ns
LVTTL_S8 1.26 1.34 1.41 1.53 3.54 3.66 3.92 3.92 3.56 3.69 3.93 3.93 ns
LVTTL_S12 1.261.341.411.533.523.653.903.903.543.683.913.91 ns
LVTTL_S16 1.261.341.411.533.073.193.453.453.093.223.463.46 ns
LVTTL_S24 1.261.341.411.533.293.413.673.673.313.443.683.68 ns
LVTTL_F4 1.26 1.34 1.41 1.53 3.26 3.38 3.64 3.64 3.28 3.41 3.65 3.65 ns
LVTTL_F8 1.26 1.34 1.41 1.53 2.74 2.87 3.12 3.12 2.76 2.90 3.13 3.13 ns
LVTTL_F12 1.261.341.411.532.732.853.103.102.742.883.123.12 ns
LVTTL_F16 1.261.341.411.532.562.682.932.932.572.712.952.95 ns
LVTTL_F24 1.261.341.411.532.522.652.903.232.542.682.913.24 ns
LVDS_25 0.730.810.880.891.291.411.671.671.311.441.681.68 ns
MINI_LVDS_25 0.73 0.81 0.88 0.89 1.27 1.40 1.65 1.65 1.29 1.43 1.66 1.66 ns
BLVDS_25 0.73 0.81 0.88 0.88 1.84 1.96 2.21 2.76 1.85 1.99 2.23 2.77 ns
RSDS_25
(point to point)
0.73 0.81 0.88 0.89 1.27 1.40 1.65 1.65 1.29 1.43 1.66 1.66 ns
PPDS_25 0.73 0.81 0.88 0.89 1.29 1.41 1.67 1.67 1.31 1.44 1.68 1.68 ns
TMDS_33 0.730.810.880.921.411.541.791.791.431.571.801.80 ns
PCI33_3 1.24 1.32 1.39 1.52 3.10 3.22 3.48 3.48 3.12 3.25 3.49 3.49 ns
HSUL_12_S 0.67 0.75 0.82 0.88 1.81 1.93 2.18 2.18 1.82 1.96 2.20 2.20 ns
HSUL_12_F 0.67 0.75 0.82 0.88 1.29 1.41 1.67 1.67 1.31 1.44 1.68 1.68 ns
DIFF_HSUL_12_S 0.68 0.76 0.83 0.86 1.81 1.93 2.18 2.18 1.82 1.96 2.20 2.20 ns
DIFF_HSUL_12_F 0.68 0.76 0.83 0.86 1.29 1.41 1.67 1.67 1.31 1.44 1.68 1.68 ns
MOBILE_DDR_S 0.760.840.910.911.681.802.062.061.701.832.072.07 ns
MOBILE_DDR_F 0.760.840.910.911.381.511.761.761.401.541.771.77 ns
DIFF_MOBILE_DDR_S 0.70 0.78 0.85 0.85 1.70 1.82 2.07 2.07 1.71 1.85 2.09 2.09 ns
DIFF_MOBILE_DDR_F 0.70 0.78 0.85 0.85 1.45 1.57 1.82 1.82 1.46 1.60 1.84 1.84 ns
HSTL_I_S 0.67 0.75 0.82 0.86 1.62 1.74 1.99 1.99 1.63 1.77 2.01 2.01 ns
HSTL_II_S 0.65 0.73 0.80 0.86 1.41 1.54 1.79 1.79 1.43 1.57 1.80 1.81 ns