Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 37
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 54 shows the test setup parameters used for measuring input delay.
Table 53: IOB 3-state Output Switching Characteristics
Symbol Description
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
T
IOTPHZ
T input to pad high-impedance 2.06 2.19 2.37 2.37 ns
T
IOIBUFDISABLE
IBUF turn-on time from IBUFDISABLE to O output 2.11 2.30 2.60 2.60 ns
Table 54: Input Delay Measurement Methodology
Description I/O Standard Attribute V
L
(1)(2)
V
H
(1)(2)
V
MEAS
(1)(4)(6)
V
REF
(1)(3)(5)
LVCMOS, 1.2V LVCMOS12 0.1 1.1 0.6 –
LVCMOS, 1.5V LVCMOS15 0.1 1.4 0.75 –
LVCMOS, 1.8V LVCMOS18 0.1 1.7 0.9 –
LVCMOS, 2.5V LVCMOS25 0.1 2.4 1.25 –
LVCMOS, 3.3V LVCMOS33 0.1 3.2 1.65 –
LVTTL, 3.3V LVTTL 0.1 3.2 1.65 –
MOBILE_DDR, 1.8V MOBILE_DDR 0.1 1.7 0.9 –
PCI33, 3.3V PCI33_3 0.1 3.2 1.65 –
HSTL (High-Speed Transceiver Logic), Class I, 1.2V HSTL_I_12 V
REF
–0.5 V
REF
+0.5 V
REF
0.60
HSTL, Class I & II, 1.5V HSTL_I, HSTL_II V
REF
–0.65 V
REF
+0.65 V
REF
0.75
HSTL, Class I & II, 1.8V HSTL_I_18, HSTL_II_18 V
REF
–0.8 V
REF
+0.8 V
REF
0.90
HSUL (High-Speed Unterminated Logic), 1.2V HSUL_12 V
REF
–0.5 V
REF
+0.5 V
REF
0.60
SSTL (Stub Terminated Transceiver Logic), 1.2V SSTL12 V
REF
–0.5 V
REF
+0.5 V
REF
0.60
SSTL, 1.35V SSTL135, SSTL135_R V
REF
– 0.575 V
REF
+ 0.575 V
REF
0.675
SSTL, 1.5V SSTL15, SSTL15_R V
REF
–0.65 V
REF
+0.65 V
REF
0.75
SSTL, Class I & II, 1.8V SSTL18_I, SSTL18_II V
REF
–0.8 V
REF
+0.8 V
REF
0.90
DIFF_MOBILE_DDR, 1.8V DIFF_MOBILE_DDR 0.9 – 0.125 0.9 + 0.125 0
(6)
–
DIFF_HSTL, Class I, 1.2V DIFF_HSTL_I_12 0.6 – 0.125 0.6 + 0.125 0
(6)
–
DIFF_HSTL, Class I & II,1.5V DIFF_HSTL_I,
DIFF_HSTL_II
0.75 – 0.125 0.75 + 0.125 0
(6)
–
DIFF_HSTL, Class I & II, 1.8V DIFF_HSTL_I_18,
DIFF_HSTL_II_18
0.9 – 0.125 0.9 + 0.125 0
(6)
–
DIFF_HSUL, 1.2V DIFF_HSUL_12 0.6 – 0.125 0.6 + 0.125 0
(6)
–
DIFF_SSTL, 1.2V DIFF_SSTL12 0.6 – 0.125 0.6 + 0.125 0
(6)
–
DIFF_SSTL135/DIFF_SSTL135_R, 1.35V DIFF_SSTL135,
DIFF_SSTL135_R
0.675 – 0.125 0.675 + 0.125 0
(6)
–
DIFF_SSTL15/DIFF_SSTL15_R, 1.5V DIFF_SSTL15,
DIFF_SSTL15_R
0.75 – 0.125 0.75 + 0.125 0
(6)
–
DIFF_SSTL18_I/DIFF_SSTL18_II, 1.8V DIFF_SSTL18_I,
DIFF_SSTL18_II
0.9 – 0.125 0.9 + 0.125 0
(6)
–
LVDS (Low-Voltage Differential Signaling), 1.8V LVDS 0.9 – 0.125 0.9 + 0.125 0
(6)
–