Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 39
Parameters V
REF
, R
REF
, C
REF
, and V
MEAS
fully describe the test conditions for each I/O standard. The most accurate prediction
of propagation delay in any given application can be obtained through IBIS simulation, using this method:
1. Simulate the output driver of choice into the generalized test setup using values from Table 55.
2. Record the time to V
MEAS
.
3. Simulate the output driver of choice into the actual PCB trace and load using the appropriate IBIS model or capacitance
value to represent the load.
4. Record the time to V
MEAS
.
5. Compare the results of step 2 and step 4. The increase or decrease in delay yields the actual propagation delay of the
PCB trace.
Table 55: Output Delay Measurement Methodology
Description I/O Standard Attribute
R
REF
(Ω)
C
REF
(1)
(pF)
V
MEAS
(V)
V
REF
(V)
LVCMOS, 1.2V LVCMOS12 1M 0 0.6 0
LVCMOS/LVDCI/HSLVDCI, 1.5V LVCMOS15, LVDCI_15, HSLVDCI_15 1M 0 0.75 0
LVCMOS/LVDCI/HSLVDCI, 1.8V LVCMOS18, LVDCI_15, HSLVDCI_18 1M 0 0.9 0
LVCMOS, 2.5V LVCMOS25 1M 0 1.25 0
LVCMOS, 3.3V LVCMOS33 1M 0 1.65 0
LVTTL, 3.3V LVTTL 1M 0 1.65 0
PCI33, 3.3V PCI33_3 25 10 1.65 0
HSTL (High-Speed Transceiver Logic), Class I, 1.2V HSTL_I_12 50 0 V
REF
0.6
HSTL, Class I, 1.5V HSTL_I 50 0 V
REF
0.75
HSTL, Class II, 1.5V HSTL_II 25 0 V
REF
0.75
HSTL, Class I, 1.8V HSTL_I_18 50 0 V
REF
0.9
HSTL, Class II, 1.8V HSTL_II_18 25 0 V
REF
0.9
HSUL (High-Speed Unterminated Logic), 1.2V HSUL_12 50 0 V
REF
0.6
SSTL12, 1.2V SSTL12 50 0 V
REF
0.6
SSTL135/SSTL135_R, 1.35V SSTL135, SSTL135_R 50 0 V
REF
0.675
SSTL15/SSTL15_R, 1.5V SSTL15, SSTL15_R 50 0 V
REF
0.75
SSTL (Stub Series Terminated Logic),
Class I & Class II, 1.8V
SSTL18_I, SSTL18_II 50 0 V
REF
0.9
DIFF_MOBILE_DDR, 1.8V DIFF_MOBILE_DDR 50 0 V
REF
0.9
DIFF_HSTL, Class I, 1.2V DIFF_HSTL_I_12 50 0 V
REF
0.6
DIFF_HSTL, Class I & II, 1.5V DIFF_HSTL_I, DIFF_HSTL_II 50 0 V
REF
0.75
DIFF_HSTL, Class I & II, 1.8V DIFF_HSTL_I_18, DIFF_HSTL_II_18 50 0 V
REF
0.9
DIFF_HSUL_12, 1.2V DIFF_HSUL_12 50 0 V
REF
0.6
DIFF_SSTL12, 1.2V DIFF_SSTL12 50 0 V
REF
0.6
DIFF_SSTL135/DIFF_SSTL135_R, 1.35V DIFF_SSTL135, DIFF_SSTL135_R 50 0 V
REF
0.675
DIFF_SSTL15/DIFF_SSTL15_R, 1.5V DIFF_SSTL15, DIFF_SSTL15_R 50 0 V
REF
0.75
DIFF_SSTL18, Class I & II, 1.8V DIFF_SSTL18_I, DIFF_SSTL18_II 50 0 V
REF
0.9
LVDS (Low-Voltage Differential Signaling), 1.8V LVDS 100 0 0
(2)
0
LVDS, 2.5V LVDS_25 100 0 0
(2)
0
BLVDS (Bus LVDS), 2.5V BLVDS_25 100 0 0
(2)
0
Mini LVDS, 2.5V MINI_LVDS_25 100 0 0
(2)
0
PPDS_25 PPDS_25 100 0 0
(2)
0