Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 42
Output Serializer/Deserializer Switching Characteristics
Input/Output Delay Switching Characteristics
Table 59: OSERDES Switching Characteristics
Symbol Description
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
Setup/Hold
T
OSDCK_D
/
T
OSCKD_D
D input setup/hold with respect to CLKDIV
0.42/0.03 0.45/0.03 0.63/0.03 0.63/0.08 ns
T
OSDCK_T
/
T
OSCKD_T
(1)
T input setup/hold with respect to CLK
0.69/–0.13 0.73/–0.13 0.88/–0.13 0.88/–0.13 ns
T
OSDCK_T2
/
T
OSCKD_T2
(1)
T input setup/hold with respect to CLKDIV
0.31/–0.13 0.34/–0.13 0.39/–0.13 0.39/–0.13 ns
T
OSCCK_OCE
/
T
OSCKC_OCE
OCE input setup/hold with respect to CLK
0.32/0.58 0.34/0.58 0.51/0.58 0.51/0.58 ns
T
OSCCK_S
SR (reset) input setup with respect to CLKDIV 0.47 0.52 0.85 0.85 ns
T
OSCCK_TCE
/
T
OSCKC_TCE
TCE input setup/hold with respect to CLK
0.32/0.01 0.34/0.01 0.51/0.01 0.51/0.10 ns
Sequential Delays
T
OSCKO_OQ
Clock to out from CLK to OQ 0.40 0.42 0.48 0.48 ns
T
OSCKO_TQ
Clock to out from CLK to TQ 0.47 0.49 0.56 0.56 ns
Combinatorial
T
OSDO_TTQ
T input to TQ out 0.83 0.92 1.11 1.11 ns
Notes:
1. T
OSDCK_T2
and T
OSCKD_T2
are reported as T
OSDCK_T
/T
OSCKD_T
in the timing report.
Table 60: Input Delay Switching Characteristics
Symbol Description
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
IDELAYCTRL
T
DLYCCO_RDY
Reset to ready for IDELAYCTRL 3.67 3.67 3.67 3.67 µs
F
IDELAYCTRL_REF
Attribute REFCLK frequency = 200.0
(1)
200 200 200 200 MHz
Attribute REFCLK frequency = 300.0
(1)
300 300 N/A N/A MHz
Attribute REFCLK frequency = 400.0
(1)
400 400 N/A N/A MHz
IDELAYCTRL_
REF_PRECISION
REFCLK precision ±10 ±10 ±10 ±10 MHz
T
IDELAYCTRL_RPW
Minimum reset pulse width 59.28 59.28 59.28 59.28 ns
IDELAY
T
IDELAYRESOLUTION
IDELAY chain delay resolution 1/(32 x 2 x F
REF
)ps