Datasheet
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 43
T
IDELAYPAT_JIT
and
T
ODELAYPAT_JIT
Pattern dependent period jitter in delay chain for
clock pattern.
(2)
0 0 0 0 ps per tap
Pattern dependent period
jitter in delay chain for
random data pattern
(PRBS 23)
(3)
REFCLK 200 MHz ±5 ±5 ±5 ±5 ps per tap
REFCLK 300 MHz ±3.33 ±3.33 ±3.33 N/A ps per tap
REFCLK 400 MHz ±2.50 ±2.50 N/A N/A ps per tap
Pattern dependent period
jitter in delay chain for
random data pattern
(PRBS 23)
(4)
REFCLK 200 MHz ±9.0 ±9.0 ±9.0 ±9.0 ps per tap
REFCLK 300 MHz ±6.0 ±6.0 ±6.0 N/A ps per tap
REFCLK 400 MHz ±4.5 ±4.5 N/A N/A ps per tap
T
IDELAY_CLK_MAX
Maximum frequency of CLK input to IDELAY 680.00 680.00 600.00 600.00 MHz
T
IDCCK_CE
/ T
IDCKC_CE
CE pin setup/hold with respect to C for IDELAY 0.12/0.11 0.16/0.13 0.21/0.16 0.21/0.16 ns
T
IDCCK_INC
/ T
IDCKC_INC
INC pin setup/hold with respect to C for IDELAY 0.12/0.16 0.14/0.18 0.16/0.22 0.16/0.23 ns
T
IDCCK_RST
/ T
IDCKC_RST
RST pin setup/hold with respect to C for IDELAY 0.15/0.09 0.16/0.11 0.18/0.14 0.18/0.14 ns
T
IDDO_IDATAIN
Propagation delay through IDELAY Note 5 Note 5 Note 5 Note 5 ps
Notes:
1. Average tap delay at 200 MHz = 78 ps, at 300 MHz = 52 ps, and at 400 MHz = 39 ps.
2. When HIGH_PERFORMANCE mode is set to TRUE or FALSE.
3. When HIGH_PERFORMANCE mode is set to TRUE.
4. When HIGH_PERFORMANCE mode is set to FALSE.
5. Delay depends on IDELAY tap setting. See the timing report for actual values.
Table 61: IO_FIFO Switching Characteristics
Symbol Description
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
IO_FIFO Clock to Out Delays
T
OFFCKO_DO
RDCLK to Q outputs 0.55 0.60 0.68 0.68 ns
T
CKO_FLAGS
Clock to IO_FIFO flags 0.55 0.61 0.77 0.77 ns
Setup/Hold
T
CCK_D
/T
CKC_D
D inputs to WRCLK 0.47/0.02 0.51/0.02 0.58/0.02 0.58/0.18 ns
T
IFFCCK_WREN
/
T
IFFCKC_WREN
WREN to WRCLK 0.42/–0.01 0.47/–0.01 0.53/–0.01 0.53/–0.01 ns
T
OFFCCK_RDEN
/
T
OFFCKC_RDEN
RDEN to RDCLK 0.53/0.02 0.58/0.02 0.66/0.02 0.66/0.02 ns
Minimum Pulse Width
T
PWH_IO_FIFO
RESET, RDCLK, WRCLK 1.62 2.15 2.15 2.15 ns
T
PWL_IO_FIFO
RESET, RDCLK, WRCLK 1.62 2.15 2.15 2.15 ns
Maximum Frequency
F
MAX
RDCLK and WRCLK 266.67 200.00 200.00 200.00 MHz
Table 60: Input Delay Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q