Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 44
CLB Switching Characteristics
CLB Distributed RAM Switching Characteristics (SLICEM Only)
Table 62: CLB Switching Characteristics
Symbol Description
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
Combinatorial Delays
T
ILO
An – Dn LUT address to A 0.10 0.11 0.13 0.13 ns, Max
T
ILO_2
An – Dn LUT address to AMUX/CMUX 0.27 0.30 0.36 0.36 ns, Max
T
ILO_3
An – Dn LUT address to BMUX_A 0.42 0.46 0.55 0.55 ns, Max
T
ITO
An – Dn inputs to A – D Q outputs 0.94 1.05 1.27 1.27 ns, Max
T
AXA
AX inputs to AMUX output 0.62 0.69 0.84 0.84 ns, Max
T
AXB
AX inputs to BMUX output 0.58 0.66 0.83 0.83 ns, Max
T
AXC
AX inputs to CMUX output 0.60 0.68 0.82 0.82 ns, Max
T
AXD
AX inputs to DMUX output 0.68 0.75 0.90 0.90 ns, Max
T
BXB
BX inputs to BMUX output 0.51 0.57 0.69 0.69 ns, Max
T
BXD
BX inputs to DMUX output 0.62 0.69 0.82 0.82 ns, Max
T
CXC
CX inputs to CMUX output 0.42 0.48 0.58 0.58 ns, Max
T
CXD
CX inputs to DMUX output 0.53 0.59 0.71 0.71 ns, Max
T
DXD
DX inputs to DMUX output 0.52 0.58 0.70 0.70 ns, Max
Sequential Delays
T
CKO
Clock to AQ – DQ outputs 0.40 0.44 0.53 0.53 ns, Max
T
SHCKO
Clock to AMUX – DMUX outputs 0.47 0.53 0.66 0.66 ns, Max
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
T
AS
/T
AH
A
N
– D
N
input to CLK on A – D flip-flops 0.07/0.12 0.09/0.14 0.11/0.18 0.11/0.28 ns, Min
T
DICK
/T
CKDI
A
X
–D
X
input to CLK on A – D flip-flops 0.06/0.19 0.07/0.21 0.09/0.26 0.09/0.35 ns, Min
A
X
–D
X
input through MUXs and/or carry logic to
CLK on A – D flip-flops
0.59/0.08 0.66/0.09 0.81/0.11 0.81/0.20 ns, Min
T
CECK_CLB
/
T
CKCE_CLB
CE input to CLK on A – D flip-flops 0.15/0.00 0.17/0.00 0.21/0.01 0.21/0.13 ns, Min
T
SRCK
/T
CKSR
SR input to CLK on A – D flip-flops 0.38/0.03 0.43/0.04 0.53/0.05 0.53/0.18 ns, Min
Set/Reset
T
SRMIN
SR input minimum pulse width 0.52 0.78 1.04 1.04 ns, Min
T
RQ
Delay from SR input to AQ – DQ flip-flops 0.53 0.59 0.71 0.71 ns, Max
T
CEO
Delay from CE input to AQ – DQ flip-flops 0.52 0.58 0.70 0.70 ns, Max
F
TOG
Toggle frequency (for export control) 1412 1286 1098 1098 MHz
Table 63: CLB Distributed RAM Switching Characteristics
Symbol Description
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
Sequential Delays
T
SHCKO
(1)
Clock to A – B outputs 0.98 1.09 1.32 1.32 ns, Max
T
SHCKO_1
Clock to AMUX – BMUX outputs 1.37 1.53 1.86 1.86 ns, Max