Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 45
CLB Shift Register Switching Characteristics (SLICEM Only)
Setup and Hold Times Before/After Clock CLK
T
DS_LRAM
/
T
DH_LRAM
A – D inputs to CLK
0.54/0.28 0.60/0.30 0.72/0.35 0.72/0.37 ns, Min
T
AS_LRAM
/
T
AH_LRAM
Address An inputs to clock 0.27/0.55 0.30/0.60 0.37/0.70 0.37/0.71 ns, Min
Address An inputs through MUXs and/or carry
logic to clock
0.69/0.18 0.77/0.21 0.94/0.26 0.94/0.35 ns, Min
T
WS_LRAM
/
T
WH_LRAM
WE input to clock
0.38/0.10 0.43/0.12 0.53/0.17 0.53/0.17 ns, Min
T
CECK_LRAM
/
T
CKCE_LRAM
CE input to CLK
0.39/0.10 0.44/0.11 0.53/0.17 0.53/0.17 ns, Min
Clock CLK
T
MPW_LRAM
Minimum pulse width 1.05 1.13 1.25 1.25 ns, Min
T
MCP
Minimum clock period 2.10 2.26 2.50 2.50 ns, Min
Notes:
1. T
SHCKO
also represents the CLK to XMUX output. Refer to the timing report for the CLK to XMUX path.
Table 64: CLB Shift Register Switching Characteristics
Symbol Description
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
Sequential Delays
T
REG
Clock to A – D outputs
1.19 1.33 1.61 1.61
ns, Max
T
REG_MUX
Clock to AMUX – DMUX output
1.58 1.77 2.15 2.15
ns, Max
T
REG_M31
Clock to DMUX output via M31 output
1.12 1.23 1.46 1.46
ns, Max
Setup and Hold Times Before/After Clock CLK
T
WS_SHFREG
/
T
WH_SHFREG
WE input 0.37/0.10 0.41/0.12 0.51/0.17 0.51/0.17 ns, Min
T
CECK_SHFREG
/
T
CKCE_SHFREG
CE input to CLK 0.37/0.10 0.42/0.11 0.52/0.17 0.52/0.17 ns, Min
T
DS_SHFREG
/
T
DH_SHFREG
A – D inputs to CLK 0.33/0.34 0.37/0.37 0.44/0.43 0.44/0.44 ns, Min
Clock CLK
T
MPW_SHFREG
Minimum pulse width
0.77 0.86 0.98 0.98
ns, Min
Table 63: CLB Distributed RAM Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q