Datasheet
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 47
T
RCCK_EN
/
T
RCKC_EN
Block RAM enable (EN) input 0.35/0.20 0.39/0.21 0.45/0.23 0.45/0.41 ns, Min
T
RCCK_REGCE
/
T
RCKC_REGCE
CE input of output register 0.24/0.15 0.29/0.15 0.36/0.16 0.36/0.39 ns, Min
T
RCCK_RSTREG
/
T
RCKC_RSTREG
Synchronous RSTREG input 0.29/0.07 0.32/0.07 0.35/0.07 0.35/0.17 ns, Min
T
RCCK_RSTRAM
/
T
RCKC_RSTRAM
Synchronous RSTRAM input 0.32/0.42 0.34/0.43 0.36/0.46 0.36/0.57 ns, Min
T
RCCK_WEA
/
T
RCKC_WEA
Write enable (WE) input (block RAM only) 0.44/0.18 0.48/0.19 0.54/0.20 0.54/0.42 ns, Min
T
RCCK_WREN
/
T
RCKC_WREN
WREN FIFO inputs 0.46/0.30 0.46/0.35 0.47/0.43 0.47/0.43 ns, Min
T
RCCK_RDEN
/
T
RCKC_RDEN
RDEN FIFO inputs 0.42/0.30 0.43/0.35 0.43/0.43 0.43/0.62 ns, Min
Reset Delays
T
RCO_FLAGS
Reset RST to FIFO flags/pointers
(10)
0.90 0.98 1.10 1.10 ns, Max
T
RREC_RST
/
T
RREM_RST
FIFO reset recovery and removal timing
(11)
1.87/–0.81 2.07/–0.81 2.37/–0.81 2.37/–0.58 ns, Max
Maximum Frequency
F
MAX_BRAM_WF_NC
Block RAM (write first and no change modes)
When not in SDP RF mode.
509.68 460.83 388.20 388.20 MHz
F
MAX_BRAM_RF_PERFORMA
NCE
Block RAM (read first, performance mode)
When in SDP RF mode but no address overlap
between port A and port B.
509.68 460.83 388.20 388.20 MHz
F
MAX_BRAM_RF_DELAYED_
WRITE
Block RAM (read first, delayed write mode)
When in SDP RF mode and there is possibility
of overlap between port A and port B
addresses.
447.63 404.53 339.67 339.67 MHz
F
MAX_CAS_WF_NC
Block RAM cascade (write first, no change
mode)
When cascade but not in RF mode.
467.07 418.59 345.78 345.78 MHz
F
MAX_CAS_RF_PERFORMAN
CE
Block RAM cascade
(read first, performance mode)
When in cascade with RF mode and no
possibility of address overlap/one port is
disabled.
467.07 418.59 345.78 345.78 MHz
F
MAX_CAS_RF_DELAYED_W
RITE
When in cascade RF mode and there is a
possibility of address overlap between port A
and port B.
405.35 362.19 297.35 297.35 MHz
Table 65: Block RAM and FIFO Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q