Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 48
F
MAX_FIFO
FIFO in all modes without ECC 509.68 460.83 388.20 388.20 MHz
F
MAX_ECC
Block RAM and FIFO in ECC configuration 410.34 365.10 297.53 297.53 MHz
Notes:
1. The timing report shows all of these parameters as T
RCKO_DO
.
2. T
RCKO_DOR
includes T
RCKO_DOW
, T
RCKO_DOPR
, and T
RCKO_DOPW
as well as the B port equivalent timing parameters.
3. These parameters also apply to synchronous FIFO with DO_REG = 0.
4. T
RCKO_DO
includes T
RCKO_DOP
as well as the B port equivalent timing parameters.
5. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.
6. T
RCKO_FLAGS
includes the following parameters: T
RCKO_AEMPTY
, T
RCKO_AFULL
, T
RCKO_EMPTY
, T
RCKO_FULL
, T
RCKO_RDERR
, and
T
RCKO_WRERR.
7. T
RCKO_POINTERS
includes both T
RCKO_RDCOUNT
and T
RCKO_WRCOUNT.
8. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is
possible.
9. These parameters include both A and B inputs as well as the parity inputs of A and B.
10. T
RCO_FLAGS
includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
11. RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock edges of the
slowest clock (WRCLK or RDCLK).
Table 65: Block RAM and FIFO Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q