Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 50
T
DSPDCK_RSTP_PREG
/
T
DSPCKD_RSTP_PREG
RSTP input to P register CLK 0.27/0.01 0.30/0.01 0.35/0.01 0.35/0.03 ns
Combinatorial Delays from Input Pins to Output Pins
T
DSPDO_A_CARRYOUT_MULT
A input to CARRYOUT output
using multiplier
3.79 4.35 5.18 5.18 ns
T
DSPDO_D_P_MULT
D input to P output using multiplier 3.72 4.26 5.07 5.07 ns
T
DSPDO_A_P
A input to P output not using
multiplier
1.53 1.75 2.08 2.08 ns
T
DSPDO_C_P
C input to P output 1.33 1.53 1.82 1.82 ns
Combinatorial Delays from Input Pins to Cascading Output Pins
T
DSPDO_{A; B}_{ACOUT; BCOUT}
{A, B} input to {ACOUT, BCOUT}
output
0.55 0.63 0.74 0.74 ns
T
DSPDO_{A, B}_CARRYCASCOUT_MULT
{A, B} input to CARRYCASCOUT
output using multiplier
4.06 4.65 5.54 5.54 ns
T
DSPDO_D_CARRYCASCOUT_MULT
D input to CARRYCASCOUT
output using multiplier
3.97 4.54 5.40 5.40 ns
T
DSPDO_{A, B}_CARRYCASCOUT
{A, B} input to CARRYCASCOUT
output not using multiplier
1.77 2.03 2.41 2.41 ns
T
DSPDO_C_CARRYCASCOUT
C input to CARRYCASCOUT
output
1.58 1.81 2.15 2.15 ns
Combinatorial Delays from Cascading Input Pins to All Output Pins
T
DSPDO_ACIN_P_MULT
ACIN input to P output using
multiplier
3.65 4.19 5.00 5.00 ns
T
DSPDO_ACIN_P
ACIN input to P output not using
multiplier
1.37 1.57 1.88 1.88 ns
T
DSPDO_ACIN_ACOUT
ACIN input to ACOUT output 0.38 0.44 0.53 0.53 ns
T
DSPDO_ACIN_CARRYCASCOUT_MULT
ACIN input to CARRYCASCOUT
output using multiplier
3.90 4.47 5.33 5.33 ns
T
DSPDO_ACIN_CARRYCASCOUT
ACIN input to CARRYCASCOUT
output not using multiplier
1.61 1.85 2.21 2.21 ns
T
DSPDO_PCIN_P
PCIN input to P output 1.11 1.28 1.52 1.52 ns
T
DSPDO_PCIN_CARRYCASCOUT
PCIN input to CARRYCASCOUT
output
1.36 1.56 1.85 1.85 ns
Clock to Outs from Output Register Clock to Output Pins
T
DSPCKO_P_PREG
CLK PREG to P output 0.33 0.37 0.44 0.44 ns
T
DSPCKO_CARRYCASCOUT_PREG
CLK PREG to CARRYCASCOUT
output
0.52 0.59 0.69 0.69 ns
Clock to Outs from Pipeline Register Clock to Output Pins
T
DSPCKO_P_MREG
CLK MREG to P output 1.68 1.93 2.31 2.31 ns
T
DSPCKO_CARRYCASCOUT_MREG
CLK MREG to CARRYCASCOUT
output
1.92 2.21 2.64 2.64 ns
T
DSPCKO_P_ADREG_MULT
CLK ADREG to P output using
multiplier
2.72 3.10 3.69 3.69 ns
T
DSPCKO_CARRYCASCOUT_ADREG_MULT
CLK ADREG to
CARRYCASCOUT output using
multiplier
2.96 3.38 4.02 4.02 ns
Table 66: DSP48E1 Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q