Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 51
Clock to Outs from Input Register Clock to Output Pins
T
DSPCKO_P_AREG_MULT
CLK AREG to P output using
multiplier
3.94 4.51 5.37 5.37 ns
T
DSPCKO_P_BREG
CLK BREG to P output not using
multiplier
1.64 1.87 2.22 2.22 ns
T
DSPCKO_P_CREG
CLK CREG to P output not using
multiplier
1.69 1.93 2.30 2.30 ns
T
DSPCKO_P_DREG_MULT
CLK DREG to P output using
multiplier
3.91 4.48 5.32 5.32 ns
Clock to Outs from Input Register Clock to Cascading Output Pins
T
DSPCKO_{ACOUT; BCOUT}_{AREG; BREG}
CLK (ACOUT, BCOUT) to {A,B}
register output
0.64 0.73 0.87 0.87 ns
T
DSPCKO_CARRYCASCOUT_
{AREG, BREG}_MULT
CLK (AREG, BREG) to
CARRYCASCOUT output using
multiplier
4.19 4.79 5.70 5.70 ns
T
DSPCKO_CARRYCASCOUT_BREG
CLK BREG to CARRYCASCOUT
output not using multiplier
1.88 2.15 2.55 2.55 ns
T
DSPCKO_CARRYCASCOUT_DREG_MULT
CLK DREG to CARRYCASCOUT
output using multiplier
4.16 4.76 5.65 5.65 ns
T
DSPCKO_CARRYCASCOUT_CREG
CLK CREG to CARRYCASCOUT
output
1.94 2.21 2.63 2.63 ns
Maximum Frequency
F
MAX
With all registers used 628.93 550.66 464.25 464.25 MHz
F
MAX_PATDET
With pattern detector 531.63 465.77 392.93 392.93 MHz
F
MAX_MULT_NOMREG
Two register multiply without
MREG
349.28 305.62 257.47 257.47 MHz
F
MAX_MULT_NOMREG_PATDET
Two register multiply without
MREG with pattern detect
317.26 277.62 233.92 233.92 MHz
F
MAX_PREADD_MULT_NOADREG
Without ADREG 397.30 346.26 290.44 290.44 MHz
F
MAX_PREADD_MULT_NOADREG_PATDET
Without ADREG with pattern
detect
397.30 346.26 290.44 290.44 MHz
F
MAX_NOPIPELINEREG
Without pipeline registers (MREG,
ADREG)
260.01 227.01 190.69 190.69 MHz
F
MAX_NOPIPELINEREG_PATDET
Without pipeline registers (MREG,
ADREG) with pattern detect
241.72 211.15 177.43 177.43 MHz
Table 66: DSP48E1 Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q