Datasheet
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 52
Clock Buffers and Networks
Table 67: Global Clock Switching Characteristics (Including BUFGCTRL)
Symbol Description
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
T
BCCCK_CE
/T
BCCKC_CE
(1)
CE pins setup/hold 0.13/0.39 0.14/0.41 0.18/0.42 0.18/0.84 ns
T
BCCCK_S
/T
BCCKC_S
(1)
S pins setup/hold 0.13/0.39 0.14/0.41 0.18/0.42 0.18/0.84 ns
T
BCCKO_O
(2)
BUFGCTRL delay from I0/I1 to O 0.08 0.09 0.11 0.11 ns
Maximum Frequency
F
MAX_BUFG
Global clock tree (BUFG) 628.00 628.00 464.00 464.00 MHz
Notes:
1. T
BCCCK_CE
and T
BCCKC_CE
must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
parameters do not apply to the BUFGMUX primitive that assures glitch-free operation. The other global clock setup and hold times are
optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between
clocks.
2. T
BGCKO_O
(BUFG delay from I0 to O) values are the same as T
BCCKO_O
values.
Table 68: Input/Output Clock Switching Characteristics (BUFIO)
Symbol Description
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
T
BIOCKO_O
Clock to out delay from I to O 1.16 1.32 1.61 1.61 ns
Maximum Frequency
F
MAX_BUFIO
I/O clock tree (BUFIO) 680.00 680.00 600.00 600.00 MHz
Table 69: Regional Clock Buffer Switching Characteristics (BUFR)
Symbol Description
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
T
BRCKO_O
Clock to out delay from I to O 0.64 0.80 1.04 1.04 ns
T
BRCKO_O_BYP
Clock to out delay from I to O with Divide
Bypass attribute set
0.35 0.41 0.54 0.54 ns
T
BRDO_O
Propagation delay from CLR to O 0.85 0.89 1.14 1.14 ns
Maximum Frequency
F
MAX_BUFR
(1)
Regional clock tree (BUFR) 420.00 375.00 315.00 315.00 MHz
Notes:
1. The maximum input frequency to the BUFR and BUFMR is the BUFIO F
MAX
frequency.
Table 70: Horizontal Clock Buffer Switching Characteristics (BUFH)
Symbol Description
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
T
BHCKO_O
BUFH delay from I to O 0.11 0.11 0.14 0.14 ns
T
BHCCK_CE
/T
BHCKC_CE
CE pin setup and hold 0.20/0.13 0.23/0.16 0.29/0.21 0.29/0.43 ns
Maximum Frequency
F
MAX_BUFH
Horizontal clock buffer (BUFH) 628.00 628.00 464.00 464.00 MHz