Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 53
MMCM Switching Characteristics
Table 71: Duty-Cycle Distortion and Clock-Tree Skew
Symbol Description Device
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
T
DCD_CLK
Global clock tree duty-cycle distortion
(1)
All 0.20 0.20 0.20 0.20 ns
T
CKSKEW
Global clock tree skew
(2)
XC7Z007S N/A 0.27 0.27 N/A ns
XC7Z012S N/A 0.39 0.42 N/A ns
XC7Z014S N/A 0.38 0.42 N/A ns
XC7Z010 0.27 0.27 0.27 N/A ns
XC7Z015 0.33 0.39 0.42 N/A ns
XC7Z020 0.33 0.38 0.42 N/A ns
XA7Z010 N/A N/A 0.27 0.27 ns
XA7Z020 N/A N/A 0.42 0.42 ns
XQ7Z020 N/A 0.38 0.42 0.42 ns
T
DCD_BUFIO
I/O clock tree duty-cycle distortion All 0.14 0.14 0.14 0.14 ns
T
BUFIOSKEW
I/O clock tree skew across one clock region All 0.03 0.03 0.03 0.03 ns
T
DCD_BUFR
Regional clock tree duty-cycle distortion All 0.18 0.18 0.18 0.18 ns
Notes:
1. These parameters represent the worst-case duty-cycle distortion observable at the pins of the device using LVDS output buffers. For cases
where other I/O standards are used, IBIS can be used to calculate any additional duty-cycle distortion that might be caused by asymmetrical
rise/fall times.
2. The T
CKSKEW
value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx Timing Analyzer
tools to evaluate application specific clock skew.
Table 72: MMCM Specification
Symbol Description
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
MMCM_F
INMAX
Maximum input clock frequency 800.00 800.00 800.00 800.00 MHz
MMCM_F
INMIN
Minimum input clock frequency 10.00 10.00 10.00 10.00 MHz
MMCM_F
INJITTER
Maximum input clock period jitter < 20% of clock input period or 1 ns Max
MMCM_F
INDUTY
Allowable input duty cycle: 10—49 MHz 25 25 25 25 %
Allowable input duty cycle: 50—199 MHz 30 30 30 30 %
Allowable input duty cycle: 200—399 MHz 35 35 35 35 %
Allowable input duty cycle: 400—499 MHz 40 40 40 40 %
Allowable input duty cycle: >500 MHz 45 45 45 45 %
MMCM_F
MIN_PSCLK
Minimum dynamic phase-shift clock frequency 0.01 0.01 0.01 0.01 MHz
MMCM_F
MAX_PSCLK
Maximum dynamic phase-shift clock frequency 550.00 500.00 450.00 450.00 MHz
MMCM_F
VCOMIN
Minimum MMCM VCO frequency 600.00 600.00 600.00 600.00 MHz
MMCM_F
VCOMAX
Maximum MMCM VCO frequency 1600.00 1440.00 1200.00 1200.00 MHz
MMCM_F
BANDWIDTH
Low MMCM bandwidth at typical
(1)
1.00 1.00 1.00 1.00 MHz
High MMCM bandwidth at typical
(1)
4.00 4.00 4.00 4.00 MHz
MMCM_T
STATPHAOFFSET
Static phase offset of the MMCM outputs
(2)
0.12 0.12 0.12 0.12 ns
MMCM_T
OUTJITTER
MMCM output jitter Note 3
MMCM_T
OUTDUTY
MMCM output clock duty-cycle precision
(4)
0.20 0.20 0.20 0.20 ns