Datasheet
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 54
MMCM_T
LOCKMAX
MMCM maximum lock time 100.00 100.00 100.00 100.00 µs
MMCM_F
OUTMAX
MMCM maximum output frequency 800.00 800.00 800.00 800.00 MHz
MMCM_F
OUTMIN
MMCM minimum output frequency
(5)(6)
4.69 4.69 4.69 4.69 MHz
MMCM_T
EXTFDVAR
External clock feedback variation < 20% of clock input period or 1 ns Max
MMCM_RST
MINPULSE
Minimum reset pulse width 5.00 5.00 5.00 5.00 ns
MMCM_F
PFDMAX
Maximum frequency at the phase frequency
detector
550.00 500.00 450.00 450.00 MHz
MMCM_F
PFDMIN
Minimum frequency at the phase frequency
detector
10.00 10.00 10.00 10.00 MHz
MMCM_T
FBDELAY
Maximum delay in the feedback path 3 ns Max or one CLKIN cycle
MMCM Switching Characteristics Setup and Hold
T
MMCMDCK_PSEN
/
T
MMCMCKD_PSEN
Setup and hold of phase-shift enable 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 ns
T
MMCMDCK_PSINCDEC
/
T
MMCMCKD_PSINCDEC
Setup and hold of phase-shift
increment/decrement
1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 ns
T
MMCMCKO_PSDONE
Phase shift clock-to-out of PSDONE 0.59 0.68 0.81 0.81 ns
Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK
T
MMCMDCK_DADDR
/
T
MMCMCKD_DADDR
DADDR setup/hold 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 ns, Min
T
MMCMDCK_DI
/
T
MMCMCKD_DI
DI setup/hold 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 ns, Min
T
MMCMDCK_DEN
/
T
MMCMCKD_DEN
DEN setup/hold 1.76/0.00 1.97/0.00 2.29/0.00 2.29/0.00 ns, Min
T
MMCMDCK_DWE
/
T
MMCMCKD_DWE
DWE setup/hold 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 ns, Min
T
MMCMCKO_DRDY
CLK to out of DRDY 0.65 0.72 0.99 0.99 ns, Max
F
DCK
DCLK frequency 200.00 200.00 200.00 200.00 MHz, Max
Notes:
1. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
2. The static offset is measured between any MMCM outputs with identical phase.
3. Values for this parameter are available in the Clocking Wizard.
See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm
.
4. Includes global clock buffer.
5. Calculated as F
VCO
/128 assuming output duty cycle is 50%.
6. When CLKOUT4_CASCADE = TRUE, MMCM_F
OUTMIN
is 0.036 MHz.
Table 72: MMCM Specification (Cont’d)
Symbol Description
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q