Datasheet
Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 56
Device Pin-to-Pin Output Parameter Guidelines
Table 74: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)
(1)
Symbol Description Device
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flops, Fast Slew Rate, without MMCM/PLL.
T
ICKOF
Clock-capable clock input and OUTFF at
pins/banks closest to the BUFGs without
MMCM/PLL (near clock region)
(2)
XC7Z007S N/A 5.68 6.65 N/A ns
XC7Z012S N/A 5.96 6.90 N/A ns
XC7Z014S N/A 6.05 7.08 N/A ns
XC7Z010 5.08 5.68 6.65 N/A ns
XC7Z015 5.34 5.96 6.90 N/A ns
XC7Z020 5.42 6.05 7.08 N/A ns
XA7Z010 N/A N/A 6.65 6.65 ns
XA7Z020 N/A N/A 7.08 7.08 ns
XQ7Z020 N/A 6.05 7.08 7.08 ns
Notes:
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Refer to the Die Level Bank Numbering Overview section of Zynq-7000 All Programmable SoC Packaging and Pinout Specification
(UG
865).
Table 75: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)
(1)
Symbol Description Device
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flops, Fast Slew Rate, without MMCM/PLL.
T
ICKOFFAR
Clock-capable clock input and OUTFF at
pins/banks farthest from the BUFGs without
MMCM/PLL (far clock region)
(2)
XC7Z007S N/A 5.68 6.65 N/A ns
XC7Z012S N/A 6.25 7.21 N/A ns
XC7Z014S N/A 6.34 7.40 N/A ns
XC7Z010 5.08 5.68 6.65 N/A ns
XC7Z015 5.60 6.25 7.21 N/A ns
XC7Z020 5.69 6.34 7.40 N/A ns
XA7Z010 N/A N/A 6.65 6.65 ns
XA7Z020 N/A N/A 7.40 7.40 ns
XQ7Z020 N/A 6.34 7.40 7.40 ns
Notes:
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Refer to the Die Level Bank Numbering Overview section of Zynq-7000 All Programmable SoC Packaging and Pinout Specification
(UG865
).