Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 58
Device Pin-to-Pin Input Parameter Guidelines
Table 79: Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks
Symbol Description Device
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.
(1)
T
PSFD
/ T
PHFD
Full delay (legacy delay or default delay)
global clock input and IFF
(2)
without
MMCM/PLL with ZHOLD_DELAY on HR
I/O banks
XC7Z007S N/A 2.13/–0.17 2.44/–0.17 N/A ns
XC7Z012S N/A 2.55/–0.18 3.03/–0.18 N/A ns
XC7Z014S N/A 2.74/–0.25 3.18/–0.25 N/A ns
XC7Z010 2.00/–0.17 2.13/–0.17 2.44/–0.17 N/A ns
XC7Z015 2.38/–0.18 2.55/–0.18 3.03/–0.18 N/A ns
XC7Z020 2.55/–0.25 2.74/–0.25 3.18/–0.25 N/A ns
XA7Z010 N/A N/A 2.44/–0.17 2.44/–0.17 ns
XA7Z020 N/A N/A 3.18/–0.25 3.18/–0.25 ns
XQ7Z020 N/A 2.74/–0.25 3.18/–0.25 3.18/–0.25 ns
Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global
clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input flip-flop or latch.
Table 80: Clock-Capable Clock Input Setup and Hold With MMCM
Symbol Description Device
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.
(1)
T
PSMMCMCC
/
T
PHMMCMCC
No delay clock-capable clock input and
IFF
(2)
with MMCM
XC7Z007S N/A 2.68/–0.62 3.22/–0.62 N/A ns
XC7Z012S N/A 2.80/–0.62 3.34/–0.62 N/A ns
XC7Z014S N/A 2.82/–0.62 3.38/–0.62 N/A ns
XC7Z010 2.36/–0.62 2.68/–0.62 3.22/–0.62 N/A ns
XC7Z015 2.47/–0.62 2.80/–0.62 3.34/–0.62 N/A ns
XC7Z020 2.48/–0.62 2.82/–0.62 3.38/–0.62 N/A ns
XA7Z010 N/A N/A 3.22/–0.62 3.22/–0.62 ns
XA7Z020 N/A N/A 3.38/–0.62 3.38/–0.62 ns
XQ7Z020 N/A 2.82/–0.62 3.38/–0.62 3.38/–0.62 ns
Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global
clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input
signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input flip-flop or latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.