Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 59
Table 81: Clock-Capable Clock Input Setup and Hold With PLL
Symbol Description Device
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 Standard.
(1)
T
PSPLLCC
/
T
PHPLLCC
No delay clock-capable clock input and
IFF
(2)
with PLL
XC7Z007S N/A 3.03/–0.19 3.64/–0.19 N/A ns
XC7Z012S N/A 3.15/–0.20 3.76/–0.20 N/A ns
XC7Z014S N/A 3.17/–0.20 3.80/–0.20 N/A ns
XC7Z010 2.67/–0.19 3.03/–0.19 3.64/–0.19 N/A ns
XC7Z015 2.78/–0.20 3.15/–0.20 3.76/–0.20 N/A ns
XC7Z020 2.79/–0.20 3.17/–0.20 3.80/–0.20 N/A ns
XA7Z010 N/A N/A 3.64/–0.19 3.64/–0.19 ns
XA7Z020 N/A N/A 3.80/–0.20 3.80/–0.20 ns
XQ7Z020 N/A 3.17/–0.20 3.80/–0.20 3.80/–0.20 ns
Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global
clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input
signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input flip-flop or latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 82: Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
Symbol Description
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
Input Setup and Hold Time Relative to a Forwarded Clock Input Pin Using BUFIO for SSTL15 Standard.
T
PSCS
/T
PHCS
Setup and hold of I/O clock –0.38/1.39 –0.38/1.55 –0.38/1.86 –0.38/1.86 ns
Table 83: Sample Window
Symbol Description
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
T
SAMP
Sampling error at receiver pins
(1)
0.59 0.64 0.70 0.70 ns
T
SAMP_BUFIO
Sampling error at receiver pins using BUFIO
(2)
0.35 0.40 0.46 0.46 ns
Notes:
1. This parameter indicates the total sampling error of the PL DDR input registers, measured across voltage, temperature, and process. The
characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements include:
- CLK0 MMCM jitter
- MMCM accuracy (phase offset)
- MMCM phase shift resolution
These measurements do not include package or clock tree skew.
2. This parameter indicates the total sampling error of the PL DDR input registers, measured across voltage, temperature, and process. The
characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of operation. These
measurements do not include package or clock tree skew.