Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 62
Table 86 summarizes the DC specifications of the clock input of the GTP transceiver. Consult the 7 Series FPGAs GTP
Transceiver User Guide (UG482
) for further details.
GTP Transceiver Switching Characteristics
Consult the 7 Series FPGAs GTP Transceiver User Guide (UG482) for further information.
Table 86: GTP Transceiver Clock DC Input Level Specification
Symbol DC Parameter Min Typ Max Units
V
IDIFF
Differential peak-to-peak input voltage 350 – 2000 mV
R
IN
Differential input resistance – 100 – Ω
C
EXT
Required external AC coupling capacitor – 100 – nF
Table 87: GTP Transceiver Performance
Symbol Description
Output
Divider
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
F
GTPMAX
Maximum GTP transceiver data rate 6.25 6.25 3.75 N/A Gb/s
F
GTPMIN
Minimum GTP transceiver data rate 0.500 0.500 0.500 N/A Gb/s
F
GTPRANGE
PLL line rate range
1 3.2–6.25 3.2–6.25 3.2–3.75 N/A Gb/s
2 1.6–3.3 1.6–3.3 1.6–3.2 N/A Gb/s
4 0.8–1.65 0.8–1.65 0.8–1.6 N/A Gb/s
8 0.5–0.825 0.5–0.825 0.5–0.8 N/A Gb/s
F
GTPPLLRANGE
GTP transceiver PLL frequency range 1.6–3.3 1.6–3.3 1.6–3.3 N/A GHz
Table 88: GTP Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Symbol Description
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
F
GTPDRPCLK
GTPDRPCLK maximum frequency 175 175 156 N/A MHz
Table 89: GTP Transceiver Reference Clock Switching Characteristics
Symbol Description Conditions
All Speed Grades
Units
Min Typ Max
F
GCLK
Reference clock frequency range 60 – 660 MHz
T
RCLK
Reference clock rise time 20% – 80% – 200 – ps
T
FCLK
Reference clock fall time 80% – 20% – 200 – ps
T
DCREF
Reference clock duty cycle Transceiver PLL only 40 – 60 %
X-Ref Target - Figure 22
Figure 22: Reference Clock Timing Parameters
ds187_19_081513
80%
20%
T
FCLK
T
RCLK