Datasheet

Zynq-7000 All Programmable SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.19) October 3, 2016 www.xilinx.com
Product Specification 63
Table 90: GTP Transceiver PLL/Lock Time Adaptation
Symbol Description Conditions
All Speed Grades
Units
Min Typ Max
T
LOCK
Initial PLL lock – – 1 ms
T
DLOCK
Clock recovery phase acquisition and
adaptation time.
After the PLL is locked to the
reference clock, this is the time it
takes to lock the clock data
recovery (CDR) to the data
present at the input.
– 50,000 2.3 x10
6
UI
Table 91: GTP Transceiver User Clock Switching Characteristics
(1)
Symbol Description Conditions
Speed Grade
Units
-3 -2 -1C/-1I/-1LI -1Q
F
TXOUT
TXOUTCLK maximum frequency 390.625 390.625 234.375
N/A
MHz
F
RXOUT
RXOUTCLK maximum frequency 390.625 390.625 234.375
N/A
MHz
F
TXIN
TXUSRCLK maximum frequency 16-bit data path 390.625 390.625 234.375
N/A
MHz
F
RXIN
RXUSRCLK maximum frequency 16-bit data path 390.625 390.625 234.375
N/A
MHz
F
TXIN2
TXUSRCLK2 maximum frequency 16-bit data path 390.625 390.625 234.375
N/A
MHz
F
RXIN2
RXUSRCLK2 maximum frequency 16-bit data path 390.625 390.625 234.375
N/A
MHz
Notes:
1. Clocking must be implemented as described in the 7 Series FPGAs GTP Transceiver User Guide (UG482).